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T8538B Datasheet

  • T8538B

  • T8538B Quad Programmable Codec

  • 44頁

  • AGERE

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Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Features
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Description
The device consists of four independent channels of
codec and digital signal processing functions on one
chip. In addition to the classic A-to-D and D-to-A con-
version, each channel provides termination imped-
ance synthesis and a hybrid balance network.
The device is controlled by a serial microprocessor
interface, and a series of bidirectional I/O leads are
provided so that this control mechanism can be uti-
lized to operate the battery feed device, ringing volt-
age switches, etc. Common data and clock paths can
be shared over any number of devices. All the filter
coefficients, signal processing, SLIC, and test fea-
tures are accessible through this interface. This
serial interface can be operated at speeds up to
16 Mbits/s.
The choice of a PCM bus is also programmable, with
any channel capable of being assigned to any time
slot. The PCM bus can be operated at speeds up to
16.384 Mbits/s, allowing for a maximum of 256 time
slots. Separate transmit and receive interfaces are
available for 4-wire bus designs, or they can be
strapped together for a 2-wire PCM bus.
The device is available in two packages.
The T8538B 64-pin TQFP features five data latches
per channel and the 100-pin TQFP features six data
latches per channel.
Both devices are pin-compatible with the T8536B 5 V
quad programmable codecs.
3.3 V operation
Per-channel programmable gains, equalization,
termination impedance, and hybrid balance
Programmable
碌-law,
linear, or A-law modes:
鈥?Up to 256 time slots per frame
鈥?Supports PCM data rates of 512 kbits/s to
16.384 Mbits/s
鈥?Double-clock mode timing compatible with
ISDN standard interfaces
Fully programmable time-slot assignment with bit
offset
Analog and digital loopback test modes
Serial microprocessor interface:
鈥?Normal and byte-by-byte control modes
鈥?Fast scan mode
Six bidirectional control leads per channel, for
SLIC and line card function control
Differential analog output:
鈥?Mates directly to SLICs, eliminating external
components
Sigma-delta converters with dither noise reduction
Quad design to minimize package count on dense
line card applications
Meets or exceeds ITU-T G.711鈥擥.712 and rele-
vant
Telcordia Technologies
TM
requirements
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