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T8502 Datasheet

  • T8502

  • T8502 and T8503 Dual PCM Codecs with Filters

  • 370.53KB

  • 16頁

  • AGERE

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Data Sheet
July 1998
T8502 and T8503 Dual PCM Codecs with Filters
Features
s
s
s
s
s
s
s
+5 V only
Two independent channels
Pin-selectable receive gain control
Pin-selectable
碌-law
or A-law companding
Automatic powerdown mode
Low-power, latch-up-free CMOS technology
鈥?40 mW/channel typical operating power
dissipation
鈥?12.5 mW/channel typical standby power
dissipation
Automatic master clock frequency selection
鈥?2.048 MHz or 4.096 MHz
Independent transmit and receive frame strobes
2.048 MHz or 4.096 MHz data rate
On-chip sample and hold, autozero, and precision
voltage reference
Differential architecture for high noise immunity
and power supply rejection
GS
X
0
VF
X
IN0
鈥?/div>
+
+2.4 V
FILTER
NETWORK
s
Meets or exceeds ITU-T G.711鈥擥.714 require-
ments and VF characteristics of D3/D4 (as per
Bellcore PUB43801)
Operating temperature range: 鈥?0
擄C
to +85
擄C
Description
The T8502 and T8503 devices are single-chip, two-
channel,
碌-law/A-law
PCM codecs with 鏗乴ters. These
integrated circuits provide analog-to-digital and
digital-to-analog conversion. They provide the
transmit and receive 鏗乴tering necessary to interface a
voice telephone circuit to a time-division multiplexed
system. These devices are packaged in both 20-pin
SOJs and 20-pin SOGs.
The T8502 differs from the T8503 in its timing mode.
The T8502 operates in the delayed timing mode
(digital data is valid one clock cycle after frame sync
goes high), and the T8503 operates in the
nondelayed timing mode (digital data valid when
frame sync goes high) (see Figures 5 and 6).
s
s
s
s
s
D
X
D
R
ENCODER
PCM
INTERFACE
FS
X
0
FS
R
0
FS
X
1
FS
R
1
GNDD
CHANNEL 0
VF
R
O0
FILTER
NETWORK
DECODER
GAIN
CONTROL
GS0
GS1
MCLK
ASEL
GS
X
1
VF
X
IN1
VF
R
O1
INTERNAL TIMING
& CONTROL
CHANNEL 1
BIAS
CIRCUITRY
&
REFERENCE
V
DD
GNDA (2)
5-3579.b
Figure 1. Block Diagram

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