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T8208 Datasheet

  • T8208

  • ATM Interconnect

  • 214頁

  • AGERE

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Advance Data Sheet
September 2001
CelXpres
TM
T8208
ATM Interconnect
1
1.1
s
Product Overview
Features
s
Programmable priority for control/data cells trans-
mission onto cell bus
Microprocessor access to all headers of control
cell
Ability to clear counters on read
Simplified looping to any system device with a sin-
gle register programming
UTOPIA clock sourcing with additional settings
Programmable operations and maintenance and
resource management (OAM/RM) cell routing
Support of multicast and broadcast cells per PHY
Optional monitoring of misrouted cells
Counters for dropped cells per queue
Digital loopback before cell bus
Microprocessor interface, supporting both
Motor-
ola
廬
and
Intel
廬
modes (multiplexed and nonmulti-
plexed)
Control cell transmission and reception through
microprocessor port
Single 3.3 V power supply
3.3 V TTL I/O (5 V tolerant)
272-pin plastic ball grid array (PBGA) package
Industrial temperature range (鈥?0
擄C
to +85
擄C)
Hot insertion capability
Eight GPIO pins
JTAG support
Compatible with
Transwitch CellBus
廬
s
OC-12 data throughput on UTOPIA (16-bit)
(independently on RX and TX UTOPIA)
Shared UTOPIA mode
UTOPIA Level 1 and 2 (8-bit/16-bit) cell-level
handshake interface (ATM or PHY layers)
Multi-PHY (MPHY) operation
Programmable ATM layer supports up to 64 PHY
ports
Egress SDRAM buffer support to extend UTOPIA
output priority queues for 32K to 512K cells:
鈥?128 queues configurable up to four queues per
PHY with programmable sizes
鈥?Programmable number of UTOPIA output
queues with four levels of priority
Support of ATM traffic management via partial
packet discard (PPD), forward explicit congestion
notification (FECN), and the cell loss priority (CLP)
bit
Programmable slew rate GTL+ I/O:
鈥?Programmable as bus arbiter
鈥?1.7 Gbits/s cell bus operation
Flexible per port cell counters
Cell header insertion with virtual path identifier
(VPI) and virtual channel identifier (VCI) translation
via external SRAM (up to 64K entries)
Support of network node interface (NNI) and user
network interface (UNI) header types with optional
generic flow-control (GFC) insertion
Optional sourcing of cell bus clocks from device
LUT bypass option
TX UTOPIA cell buffer increased to 256 cells for
better queue management with SDRAM queue
bypass option
Ability for cell bus arbiter to mask devices on the
cell bus
Ability to modify cell bus priority based on RX PHY
FIFO thresholds
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1.2
s
Applications
Asymmetric digital subscriber line (ADSL) digital
subscriber line access multiplexers (DSLAMs)
Access gateways
Access multiplexers/concentrators
Multiservice platforms
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