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T7504 Datasheet

  • T7504

  • T7504 and T75504 Quad PCM Codecs with Filters

  • 18頁(yè)

  • AGERE

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Data Sheet
March 1999
T7504 and T5504 Quad PCM Codecs with Filters
Features
s
s
s
s
Operating temperature range: 鈥?0
擄
C to +85
擄
C
碌
-law/A-law companding selectable
5 V only
Low-power, latch-up-free CMOS technology
鈥?37 mW/channel typical operating power
dissipation
鈥?1 mW/channel typical powerdown dissipation
Automatic master clock frequency selection
鈥?2.048 MHz or 4.096 MHz
On-chip sample and hold, autozero, and precision
voltage reference
Differential architecture for high noise immunity
and power supply rejection
Flexible time-slotted PCM interface
鈥?2.048 MHz or 4.096 MHz data rate
Meets or exceeds ITU-T G.711鈥擥.714 require-
ments and VF characteristics of D3/D4 (as per
Lucent Technologies PUB43801)
Description
The T7504 and T5504 devices are single-chip, four-
channel
碌
-law/A-law PCM codecs with 鏗乴ters. These
integrated circuits provide analog-to-digital and
digital-to-analog conversion. They provide the
transmit and receive 鏗乴tering necessary to interface a
voice telephone circuit to a time-division multiplexed
system. These devices are available in 28-pin
PLCCs. The T7504 is also available in a 44-pin
MQFP.
The T5504 differs from the T7504 in its timing mode.
The T5504 operates in the nondelay timing mode
(digital data valid when frame sync goes high), and
the T7504 operates in the delayed timing mode
(digital data is valid one clock cycle after frame sync
goes high) (see Figures 6鈥?).
s
s
s
s
s
GS
X
0
VF
X
IN0
鈥?/div>
+
+2.4 V
FILTER
NETWORK
D
X
D
R
ENCODER
PCM
INTERFACE
FS
X
0
FS
X
1
FS
X
2
FS
X
3
FSEP
GNDD
CHANNEL 0
VF
R
O0
FILTER
NETWORK
DECODER
POWERDOWN
CONTROL
INTERNAL TIMING
& CONTROL
MCLK
ASEL
V
DD
(2)
GS
X
1
VF
X
INF1
VF
R
O1
GS
X
2
VF
X
IN2
VF
R
O2
GS
X
3
VF
X
IN3
VF
R
O3
CHANNEL 1
CHANNEL 2
CHANNEL 3
BIAS
CIRCUITRY
&
REFERENCE
V
DD
(2) (MQFP ONLY)
GNDA (4) (PLCC ONLY)
GNDA (5) (MQFP ONLY)
5-3579.d(C)
Figure 1. Block Diagram For 28-Pin DIP and 28-Pin PLCC

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