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SY89871U Datasheet

  • SY89871U

  • 2.5GHz ANY DIFF. IN-TO-LVPECL PROGRAMMABLE CLOCK DIVIDER/ FA...

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  • MICREL   MICREL

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Micrel
2.5GHz ANY DIFF. IN-TO-LVPECL
SY89871U
Precision Edge鈩?/div>
PROGRAMMABLE CLOCK DIVIDER/
SY89871U
FANOUT BUFFER W/INTERNAL TERMINATION
Precision Edge鈩?/div>
FEATURES
s
Two matched-delay outputs:
鈥?Bank A: undivided pass-through (QA)
鈥?Bank B: programmable divide by
2, 4, 8, 16 (QB0, QB1)
s
Matched delay: all outputs have matched delay,
independent of divider setting
s
Guaranteed AC performance:
鈥?>2.5GHz f
MAX
鈥?<250ps t
r
/t
f
鈥?<670ps t
pd
(matched delay)
鈥?<15ps within-device skew
s
Low jitter design
鈥?<1ps
rms
cycle-to-cycle jitter
鈥?<10ps
pp
total jitter
s
Power supply 3.3V or 2.5V
s
Unique patent-pending input termination and VT pin
for DC-coupled and AC-coupled inputs: any
differential inputs (LVPECL, LVDS, CML, HSTL)
s
TTL/CMOS inputs for select and reset
s
100K EP compatible LVPECL outputs
s
Parallel programming capability
s
Wide operating temperature range: 鈥?0
擄
C to +85
擄
C
s
Available in 16-pin (3mm
脳
3mm) MLF鈩?package
Precision Edge鈩?/div>
DESCRIPTION
The SY89871U is a 2.5V/3.3V LVPECL output precision
clock divider capable of accepting a high-speed differential
clock input (AC or DC-coupled) CML, LVPECL, HSTL or
LVDS clock input signal and dividing down the frequency
using a programmable divider ratio to create a frequency-
locked lower speed version of the input clock (Bank B).
Available divider ratios are 2, 4, 8 and 16. In a typical
622MHz clock system this would provide availability of
311MHz, 155MHz, 77MHz, or 38MHz auxiliary clock
components.
The differential input buffer has a unique internal
termination design that allows access to the termination
network through a VT pin. This feature allows the device to
easily interface to different logic standards. A V
REF-AC
reference is included for AC-coupled applications.
The SY89871U includes two phase-matched output
banks. Bank A (QA) is a frequency-matched copy of the
input. Bank B (QB0, QB1) is a divided down output of the
input frequency. Bank A and Bank B maintain a matched
delay independent of the divider setting.
All support documentation can be found on Micrel鈥檚 web
site at www.micrel.com.
APPLICATIONS
s
s
s
s
OC-3 to OC-192 SONET/SDH applications
Transponders
Oscillators
SONET/SDH line cards
FUNCTIONAL BLOCK DIAGRAM
QA
V
REF-AC
TYPICAL PERFORMANCE
/QA
QA
QA@622MHz and QB@155.5MHz
QB0
IN
50鈩?/div>
V
T
50鈩?/div>
/IN
Divided
by
2, 4, 8
or 16
622MHz
Output
/QA
/QB0
QB1
/QB1
QB0
S0
155.5MHz
Decoder
S1
脰4
Output
/QB0
/RESET
Precision Edge is a trademark of Micrel, Inc.
Micro
LeadFrame and MLF are trademarks of Amkor Technology, Inc.
M9999-062904
hbwhelp@micrel.com or (408) 955-1690
Rev.: C
Amendment: /0
1
Issue Date: June 2004

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