ClockWorks鈩?/div>
SY89824L
DESCRIPTION
The SY89824L is a High Performance Bus Clock Driver
with 22 differential HSTL (High Speed Transceiver Logic)
output pairs. The part is designed for use in low voltage
(3.3V/1.8V) applications which require a large number of
outputs to drive precisely aligned, ultra low skew signals to
their destination. The input is multiplexed from either HSTL
or LVPECL (Low Voltage Positive Emitter Coupled Logic)
by the CLK_SEL pin. The Output Enable (OE) is
synchronous so that the outputs will only be enabled/
disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when
the device is enabled/disabled as can happen with an
asynchronous control.
The SY89824L features low pin-to-pin skew (50ps max.)
and low part-to-part skew (200ps max.)鈥攑erformance
previously unachievable in a standard product having such
a high number of outputs. The SY89824L is available in a
single space saving package, enabling a lower overall cost
solution.
power
s
LVPECL and HSTL inputs
s
22 differential HSTL (low-voltage swing) output pairs
s
HSTL outputs drive 50
鈩?/div>
to ground with no offset
voltage
s
Low part-to-part skew (200ps max.)
s
Low pin-to-pin skew (50ps max.)
s
Available in a 64-Pin EPAD HQFP
PIN CONFIGURATION
Q
0
Q
0
V
CCO
V
CCO
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
Q
4
Q
4
Q
5
Q
5
Q
6
Q
6
V
CCO
NC
NC
V
CCI
HSTL_CLK
HSTL_CLK
CLK_SEL
LVPECL_CLK
LVPECL_CLK
GND
OE
NC
NC
Q
21
Q
21
V
CCO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48
47
46
45
44
43
42
V
CCO
Q
7
Q
7
Q
8
Q
8
Q
9
Q
9
Q
10
Q
10
Q
11
Q
11
Q
12
Q
12
Q
13
Q
13
V
CCO
PIN NAMES
Pin
HSTL_CLK, /HSTL_CLK
LVPECL_CLK, /LVPECL_CLK
CLK_SEL
OE
Q
0
-Q
21
, /Q
0
-/Q
21
GND
V
CCI
V
CCO
Function
Differential HSTL Inputs
Differential LVPECL Inputs
Input CLK Select (LVTTL)
Output Enable (LVTTL)
Differential HSTL Outputs
Ground
V
CC
Core
V
CC
Output
64-PIN
HQFP
41
40
39
38
37
36
35
34
33
APPLICATIONS
s
High-performance PCs
s
Workstations
s
Parallel processor-based systems
s
Other high-performance computing
s
Communications
V
CCO
Q
20
Q
20
Q
19
Q
19
Q
18
Q
18
Q
17
Q
17
Q
16
Q
16
Q
15
Q
15
Q
14
Q
14
V
CCO
LOGIC SYMBOL
CLK_SEL
HSTL_CLK
HSTL_CLK
0
22
22
Q0 - Q21
Q0 - Q21
LVPECL_CLK
1
LVPECL_CLK
LEN
Q
OE
D
Rev.: C
Amendment: /1
1
Issue Date: March 2000
MICREL
1
2
3
4
