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SY89424VZCTR Datasheet

  • SY89424VZCTR

  • 5V/3.3V FREQUENCY SYNTHESIZER 60MHz to 1GHz

  • 5頁

  • MICREL   MICREL

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5V/3.3V
FREQUENCY SYNTHESIZER
(60MHz to 1GHz)
FEATURES
s
3.3V and 5V power supply options
s
Up to 1GHz clock frequencies
s
Internal quartz reference oscillator driven by quartz
crystal or PECL source
s
Low jitter PLL design
s
On-chip 20 ohm driver
s
Differential outputs with 600mV (min) swing
s
Optional pull-down resistors for AC-coupled outputs
s
Low power consumption
s
External loop filter optimizes performance/cost
s
Available in 16-pin SOIC package
ClockWorks鈩?/div>
SY89424V
DESCRIPTION
The SY89424V is a low-power Phase Locked Loop
(PLL) based frequency synthesizer. The device is capable
of generating up to 1GHz clock frequencies with a low-cost
10鈥?5MHz external series-resonant quartz crystal. One
can also use PECL differential clock signals to drive this
device instead of the quartz crystal. Operation of this chip
is controlled by three select pins (S1, S2 and S3). S1
selects the divide ratio of 24 or 50 for the PLL. S2 and S3
select the output frequency. There are two pull-down
resistor pins (PDR
1
and PDR
2
). Each pin has an on-chip
resistor that will control the output driver currents. When
PDR
1
and PDR
2
pins are open, both outputs are normal
open emitter PECL drivers. When PDR
1
and PDR
2
pins
are shorted to the outputs, on-chip pull down currents of
25mA (40mA at 5V V
CC
) are provided. Both output drivers
are capable of driving 20 ohm clock lines. An output enable
(OE) pin is available and it can be HIGH or left open for
normal operation. When OE is LOW, a built-in Disable
Timing Synchronizer will force the FOUT output to LOW at
the completion of the HIGH clock cycle. The FOUT output
remains HIGH during that time.
BLOCK DIAGRAM
F1A F2A
XTAL1
OSC
XTAL2
PHASE
COMP
CHARGE
PUMP
LOOP
FILTER
梅 24, 梅 50
VCO
S1A
梅 1, 2, 3, 4
FOUT
FOUT
PDR1 PDR2
S2A
S3A
OE
Rev.: G
Amendment: /0
1
Issue Date: May, 1998

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