SY89113U
2.5V Low Jitter, Low Skew 1:12 LVDS Fanout
Buffer with 2:1 Input MUX and Internal Termination
General Description
The SY89113U is a 2.5V low jitter, low skew, 1:12
LVDS fanout buffer optimized for precision telecom
and enterprise server distribution applications. The
input includes a 2:1 MUX for clock switchover
applications. Unlike other multiplexers, this input
includes a unique isolation design that minimizes
channel-to-channel
crosstalk.
The
SY89113U
distributes clock frequencies from DC to >1GHz
guaranteed over temperature and voltage. The
SY89113U incorporates a synchronous output enable
(EN) so that the outputs will only be enabled/disabled
when they are already in the LOW state.
CLK0 differential input includes Micrel's unique, 3-pin
input termination architecture that directly interfaces to
any differential signal (AC- or DC-coupled) as small as
100mV (200mV
PP
) without any level shifting or
termination resistor networks in the signal path.
CLK1 differential input includes a new version of
Micrel's unique, Any-Input architecture that directly
interfaces with single-ended TTL/CMOS logic
(including 3.3V logic), single-ended LVPECL,
differential (AC- or DC-coupled) LVDS, HSTL, CML,
and LVPECL logic levels as small as 200mV
(400mV
PP
). CLK1 input requires external termination.
LVDS output swing 325mV into 100鈩?with extremely
fast rise/fall time guaranteed to be less than 250ps.
The SY89113U operates from a 2.5V鹵5% supply and
is guaranteed over the full industrial temperature
range of -40擄C to +85擄C. The SY89113U is part of
Micrel's high-speed, Precision Edge
廬
product line.
All support documentation can be found on Micrel鈥檚
web site at:
www.micrel.com.
Precision Edge
廬
Features
鈥?/div>
Selects between 1 of 2 inputs, and provides 12
precision, low skew LVDS output copies
鈥?/div>
Guaranteed AC performance over temperature and
voltage:
鈥?DC to >1GHz throughput
鈥?<975ps propagation delay CLK0-to-Q
鈥?<250ps rise/fall time
鈥?<25ps output-to-output skew
鈥?/div>
Ultra-low jitter design:
鈥?<1ps
RMS
random jitter
鈥?<10ps
PP
total jitter (clock)
鈥?<1ps
RMS
cycle-to-cycle jitter
鈥?<0.7ps
RMS
crosstalk induced jitter
鈥?/div>
Unique, patent-pending 2:1 input MUX provides
superior isolation to minimize channel-to-channel
crosstalk
鈥?/div>
CLK0 input features a unique, patent-pending input
termination and VT pin that accepts AC- and DC-
coupled inputs (CML, LVPECL, LVDS)
鈥?/div>
CLK1 accepts virtually any logic standard:
鈥?Single-ended: TTL/CMOS (including 3.3V logic),
LVPECL
鈥?Differential: LVPECL, LVDS, CML, HSTL
鈥?/div>
325mV LVDS-compatible output swing
鈥?/div>
Power supply: 2.5V +5%
鈥?/div>
Industrial temperature range 鈥?0擄C to +85擄C
鈥?/div>
Available in 44-pin (7mm x 7mm) MLF鈩?package
Applications
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Precision Edge is a registered trademark of Micrel, Inc.
MLF and
MicroLeadFrame
are trademarks of Amkor Technology, Inc.
Micrel Inc. 鈥?2180 Fortune Drive 鈥?San Jose, CA 95131 鈥?USA 鈥?tel +1 (408) 944-0800 鈥?fax + 1 (408) 474-1000 鈥?http://www.micrel.com
Multi-processor server
SONET/SDH clock/data distribution
Fibre Channel distribution
Gigabit Ethernet clock distribution
March 2005
M9999-032905
hbwhelp@micrel.com
or (408) 955-1690
SY89112U相關(guān)型號(hào)PDF文件下載
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