OC-3/STS-3
CLOCK RECOVERING
TRANSCEIVER
FEATURES
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A complete SONET/SDH/ATM compatible single chip
Transmitter and Receiver
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Seamless operation with PMC-Sierra PM5345, VLSI
VNS67200, IgT WAC-013-B/WAC-413-A and NEC
碌
PD98402 UNI Processors
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Supports clock and data recovery from 51.84 Mbit/s
or 155.52 Mbit/s NRZ or NRZI data stream
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155.52MHz clock multiplication from 19.44MHz
source or 51.84MHz clock multiplication from
6.48MHz source
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Line Receiver Inputs: No external buffering needed
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Differential output buffering
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Link Status Indication
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Loop-back testing
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100K ECL compatible I/O
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Single +5 volt power supply
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Available in 28-pin SOIC package
SY69952A
DESCRIPTION
Micrel-Synergy's SY69952A contains fully integrated
transmitter and receiver functions designed to provide
clock recovery and generation for either 51.84Mbit/s OC/
STS-1 or 155.52Mbit/s OC/STS-3 SONET/SDH
(SY69952) and ATM applications.
On-chip clock generation is performed by a low-jitter
phase-locked loop (PLL) allowing use of 19.44MHz
reference for 155.52MHz generation or a 6.48MHz
reference for 51.84MHz generation. Clock recovery is
performed by synchronizing the on-chip VCO directly to
the incoming data stream.
Micrel-Synergy's circuit design techniques coupled with
ASSET鈩?bipolar technology result in ultra-fast
performance with low noise and low power dissipation.
FUNCTIONAL BLOCK DIAGRAM
PLL2+
PLL2-
PIN CONFIGURATION
LOOP
MODE
ROUT+
ROUT-
ROUT+
ROUT-
RIN+
RCLK+
RCLK-
PLL
RSER+
RSER-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
TOP VIEW
SOIC
22
21
20
19
18
17
16
15
RCLK-
RCLK+
RSER-
RSER+
LFI
V
CC
V
EE
V
CC
TCLK-
TCLK+
TSER+
TSER-
PLL2+
PLL2-
RIN+
RIN-
RIN-
MODE
V
CC
CD
LOOP
REFCLK-
REFCLK+
TOUT-
CD
LFI
RECEIVE
TRANSMIT
TOUT+
TOUT-
PLL
x8
TSER+
TSER-
TCLK+
TCLK-
TOUT+
PLL1+
PLL1-
REFCLK+
REFCLK-
PLL1+
PLL1-
Rev.: C
Amendment: /0
1
Issue Date: May 2000
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