ClockWorks鈩?/div>
PRELIMINARY
SY10H841L
SY100H841L
DESCRIPTION
The SY10/100H841L are single supply, low skew
translating 1:4 clock drivers.
The devices feature a 24mA TTL output stage, with
AC performance specified into a 20pF load capacitance.
A latch is provided on-chip. When LEN is LOW (or left
open, in which case it is pulled low by the internal pull-
downs) the latch is transparent. A HIGH on the enable
pin (EN) forces all outputs LOW.
As frequencies increase to 40MHz and above, precise
timing and shaping of clock signals becomes extremely
important. The H841 solves several clock distribution
problems such as minimizing skew (300ps), maximizing
clock fanout (24mA drive), and precise duty cycle control
through a proprietary differential internal design.
The 10K version is compatible with 10KH ECL logic
levels. The 100K version is compatible with 100K levels.
PIN CONFIGURATION
BLOCK DIAGRAM
Q
0
LEN
EN
G
E
V
E
D
1
2
3
4
5
6
7
8
SOIC
Z16-1
16
15
14
13
12
11
10
9
Q
3
G
T
Q
2
V
T
V
T
Q
1
G
T
Q
0
Q
1
D
V
BB
G
T
Q
2
V
BB
PIN NAMES
D
D
LEN
EN
D Q
Q
3
Pin
G
T
V
T
V
E
G
E
D, D
V
BB
Q
0
- Q
3
EN
LEN
1
Function
TTL Ground (0V)
TTL V
CC
(+3.3V)
ECL V
CC
(+3.3V)
ECL Ground (0V)
Signal Input (PECL)
V
BB
Reference Output (PECL)
Signal Outputs (TTL)
Enable Input (PECL)
Latch Enable Input
Rev.: C
Amendment: /0
Issue Date: May, 1999