鈩?/div>
ECL outputs
s
Choice between differential PECL or TTL clock input
s
Single +5V power supply
s
V
BB
output for single-ended use
s
Multiple power and ground pins to minimize noise
s
Specified within-device skew
s
Fully compatible with Motorola MC10H/100H606
s
Available in 28-pin PLCC package
SY10H606
SY100H606
DESCRIPTION
The SY10/100H606 are 6-bit, registered, single supply
TTL-to-PECL translators. The devices feature differential
PECL outputs as well as a choice between either a
differential PECL clock input or a TTL clock input. The
asynchronous master reset control is a PECL level input.
With its differential ECL outputs and TTL inputs, the
H606 device is ideally suited for the transmit function of
a HPPI bus-type board-to-board interface application. The
on-chip registers simplify the task of synchronizing the
data between the two boards.
The device is available in either ECL standard: the
10H device is compatible with 10K logic levels, while the
100H device is compatible with 100K logic levels.
BLOCK DIAGRAM
PIN CONFIGURATION
D
2
V
CCT
D
3
V
CCE
D
1
D
4
D
5
1 OF 6 BITS
25 24 23 22 21 20 19
D
0
D
n
D
Q
Q
n
Q
n
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
16
TCLK
V
BB
CLK
CLK
Q
5
Q
5
Q
4
Q
4
V
CCE
Q
3
Q
3
TOP VIEW
PLCC
15
14
13
12
CLK
R
MR
V
CCE
Q
0
Q
0
GND
Q
1
Q
1
CLK
CLK
TCLK
PIN NAMES
MR
Pin
V
BB
D
0
鈥?D
5
CLK, CLK
TCLK
MR
Q
0
鈥?Q
5
Q
0
鈥?Q
5
V
CCE
V
CCT
GND
V
BB
Function
TTL Data Inputs
Differential PECL Clock Inputs
TTL Clock Input
PECL Master Reset Input
True PECL Outputs
Inverted PECL Outputs
PECL V
CC
(5.0V)
TTL V
CC
(5.0V)
TTL/PECL Ground
V
BB
Reference Output (PECL)
Rev.: D
Amendment: /0
1
Q
2
Q
2
Issue Date: March, 1998
1
2
3
4
