3.3V/5V LVTTL/LVCMOS-to-
DIFFERENTIAL LVPECL
TRANSLATOR
FEATURES
s
3.3V and 5V power supply options
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300ps typical propagation delay
s
Differential LVPECL output
s
I
CC
Max 20mA
s
PNP LVTTL input for minimal loading
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Q output will default HIGH with inputs open
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High bandwidth to 800MHz typical
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Available in 8-pin MSOP and SOIC package
SY10EPT20V
SY100EPT20V
DESCRIPTION
The SY10/100EPT20V is a TTL/CMOS to differential
PECL translator. Capable of running from a 3.3 or 5V
supply, the part can be used in either LVTTL/LVCMOS/
LVPECL or TTL/CMOS/PECL systems.
The device only requires a single positive supply of
3.3V or 5V - no negative supply is required.
The tiny 8-pin MSOP package and the low skew, dual
gate design of the EPT20V makes it ideal for those
applications where space, performance, and low power
are at a premium.
PIN CONFIGURATION/BLOCK DIAGRAM
NC 1
Q 2
/Q 3
NC 4
LVPECL
LVTTL
PIN NAMES
Pin
Function
Differential LVPECL Output
LVTTL Input
Positive Supply
Ground
8 V
CC
7 D
6 NC
5 GND
Q, /Q
D
V
CC
GND
(Available in 8-pin SOIC or 8-pin MSOP)
Rev.: A
Amendment: /1
1
Issue Date: July 2000