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input pull-down resistors
s
Available in 8-pin SOIC package
DESCRIPTION
The SY10/100EL35 are high-speed JK Flip-Flops. The
J/K data enters the master portion of the flip-flop when
the clock is LOW and is transferred to the slave and,
thus, the outputs, upon a positive transition of the clock.
The reset pin is asynchronous and is activated with a
logic HIGH.
PIN CONFIGURATION/BLOCK DIAGRAM
TRUTH TABLE
(1)
J
K
L
H
L
H
X
R
L
L
L
L
H
CLK
Z
Z
Z
Z
X
Qn+1
Qn
L
H
Qn
L
J
K
CLK
R
1
2
3
J
K
8
7
6
R
5
V
CC
Q
Q
V
EE
L
L
H
H
X
4
NOTE:
1. Z = LOW-to-HIGH transition.
SOIC
TOP VIEW
Rev.: E
Amendment: /0
1
Issue Date: August, 1998