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SY10EL33ZCTR Datasheet

  • SY10EL33ZCTR

  • 5V/3.3V ± 4 DIVIDER

  • 62.08KB

  • 4頁

  • MICREL   MICREL

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5V/3.3V
梅
4 DIVIDER
ClockWorks鈩?/div>
SY10EL33/L
SY100EL33/L
FEATURES
s
3.3V and 5V power supply options
s
650ps propagation delay
s
4.0GHz toggle frequency
s
High bandwidth output transistions
s
Internal 75K
鈩?/div>
input pull-down resistors
s
Available in 8-pin SOIC package
DESCRIPTION
The SY10/100EL33/L are integrated
梅4
dividers. The
differential clock inputs and the V
BB
allow a differential,
single-ended or AC-coupled interface to the device. If
used, the V
BB
output should be bypassed to ground with
a 0.01碌F capacitor. Also note that the V
BB
is designed to
be used as an input bias on the EL33/L only; the V
BB
output has limited current sink and source capability.
The reset pin is asynchronous and is asserted on the
rising edge. Upon power-up, the internal flip-flops will
attain a random state; the reset input allows for the
synchronization of multiple EL33/Ls in a system.
PIN CONFIGURATION/BLOCK DIAGRAM
PIN NAMES
Pin
Function
Clock Inputs
Asynchronous Reset
Reference Voltage Output
Data Outputs
Reset
CLK
CLK
V
BB
CLK
1
R
2
梅
4
3
4
8
7
6
5
V
CC
Q
Q
V
EE
Reset
V
BB
Q
SOIC
TOP VIEW
Rev.: E
Amendment: /1
1
Issue Date: August 2000

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