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SY10EL32VZCTR Datasheet

  • SY10EL32VZCTR

  • 5V/3.3V ± 2 DIVIDER

  • 4頁

  • MICREL   MICREL

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5V/3.3V
梅
2 DIVIDER
ClockWorks鈩?/div>
SY10EL32V
SY100EL32V
FEATURES
s
3.3V and 5V power supply options
s
510ps propagation delay
s
3.0GHz toggle frequency
s
High bandwidth output transistions
s
Internal 75K
鈩?/div>
input pull-down resistors
s
Available in 8-pin SOIC package
DESCRIPTION
The SY10/100EL32V are integrated
梅2
dividers. The
differential clock inputs and the V
BB
allow a differential,
single-ended or AC-coupled interface to the device. If
used, the V
BB
output should be bypassed to ground with
a 0.01碌F capacitor. Also note that the V
BB
is designed to
be used as an input bias on the EL32V only; the V
BB
output has limited current sink and source capability.
The reset pin is asynchronous and is asserted on the
rising edge. Upon power-on, the internal flip-flop will attain
a random state; the reset allows for the synchronization
of multiple EL32Vs in a system.
PIN CONFIGURATION/BLOCK DIAGRAM
PIN NAMES
Pin
Function
Clock Inputs
Asynchronous Reset
Reference Voltage Output
Data Outputs
Reset
CLK
CLK
V
BB
1
R
2
梅
2
3
4
8
7
6
5
V
CC
Q
Q
V
EE
CLK
Reset
V
BB
Q
SOIC
TOP VIEW
Rev.: C
Amendment: /0
1
Issue Date: August, 1998

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