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input pull-down resistors
s
Available in 8-pin SOIC package
DESCRIPTION
The SY10/100EL31 are D flip-flops with set and reset.
The devices are functionally equivalent to the E131
devices, with higher performance capabilities. With
propagation delays and output transition times
significantly faster than the E131, the EL31 is ideally
suited for those applications which require the ultimate
in AC performance.
Both the set and reset inputs are asynchronous, level
triggered signals. Data enters the master portion of the
flip-flop when the clock is LOW and is transferred to the
slave, and thus the outputs, upon a positive transition of
the clock.
PIN CONFIGURATION/BLOCK DIAGRAM
PIN NAMES
Pin
D
Data Inputs
Data Outputs
Set
Reset
Clock Input
Function
S
D
CLK
R
1
S
2
3
R
4
D
Flip-Flop
8
7
6
5
V
CC
Q
Q
V
EE
Q
S
R
CLK
TRUTH TABLE
(1)
SOIC
TOP VIEW
D
L
H
X
X
X
S
L
L
H
L
H
R
L
L
L
H
H
CLK
Z
Z
X
X
X
Q
L
H
H
L
Undef
NOTE:
1. Z = LOW-to-HIGH transition.
Rev.: E
Amendment: /0
1
Issue Date: August, 1998