Precision Edge鈩?/div>
DESCRIPTION
The SY10/100EL15 are low skew 1:4 clock distribution
chips designed explicitly for low skew clock distribution
applications. The device can be driven by either a
differential or single-ended ECL or, if positive power
supplies are used, PECL input signal. If a single-ended
input is to be used the V
BB
output should be connected
to the CLK input and bypassed to V
CC
via a 0.01碌F
capacitor. The V
BB
output is designed to act as the
switching reference for the input of the EL15 under single-
ended input conditions, as a result this pin can only
source/sink up to 0.5mA of current.
The EL15 features a multiplexed clock input to allow
for the distribution of a lower speed scan or test clock
along with the high speed system clock. When LOW (or
left open and pulled LOW by the input pull-down resistor)
the SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the
outputs will only be enabled/disabled when they are
already in the LOW state. This avoids any chance of
generating a runt clock pulse when the device is enabled/
disabled as can happen with an asynchronous control.
The internal flip flop is clocked on the falling edge of the
input clock, therefore all associated specification limits
are referenced to the negative edge of the clock input.
PIN CONFIGURATION/BLOCK DIAGRAM
V
CC
16
EN SCLK CLK CLK V
BB
15
14
13
1
D
Q
0
12
11
SEL V
EE
10
9
1
Q
0
2
Q
0
3
Q
1
4
Q
1
5
Q
2
6
Q
2
7
Q
3
8
Q
3
SOIC
TOP VIEW
PIN NAMES
Pin
CLK
SCLK
EN
SEL
V
BB
Q
0-3
Function
Differential Clock Inputs
Synchronous Clock Input
Synchronous Enable
Clock Select Input
Reference Output
Differential Clock Outputs
TRUTH TABLE
CLK
L
H
X
X
X
SCLK
X
X
L
H
X
SEL
L
L
H
H
X
EN
L
L
L
L
H
Q
L
H
L
H
L*
* On next negative transition of CLK or SCLK
Precision Edge is a trademark of Micrel, Inc.
Rev.: G
Amendment: /0
1
Issue Date: February 2003
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