鈩?/div>
input pull-down resistors
s
Fully compatible with Motorola MC10E/100E445
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E445 are integrated 4-bit serial-to-parallel
data converters. The devices are designed to operate for
NRZ data rates of up to 2.5Gb/s. The chip generates a
divide-by-4 and a divide-by-8 clock for both 4-bit conversion
and a two-chip 8-bit conversion function. The conversion
sequence was chosen to convert the first serial bit to Q
0
,
the second to Q
1
, etc.
Two selectable serial inputs provide a loopback capability
for testing purposes when the device is used in conjunction
with the E446 parallel-to-serial converter.
The start bit for conversion can be moved using the
SYNC input. A single pulse, applied asynchronously for at
least two input clock cycles, shifts the start bit for conversion
from Q
n
to Q
n-1
by one bit. For each additional shift required,
an additional pulse must be applied to the SYNC input.
Asserting the SYNC input will force the internal clock dividers
to "swallow" a clock pulse, effectively shifting a bit from the
Q
n
to the Q
n-1
output (see Timing Diagram B).
The MODE input is used to select the conversion mode
of the device. With the MODE input LOW (or open) the
device will function as a 4-bit converter. When the mode
input is driven HIGH, the data on the output will change on
every eighth clock cycle, thus allowing for an 8-bit conversion
scheme using two E445s. When cascaded in an 8-bit
conversion scheme, the devices will not operate at the
2.5Gb/s data rate of a single device. Refer to the applications
section of this data sheet for more information on cascading
the E445.
For lower data rate applications, a V
BB
reference voltage
is supplied for single-ended inputs. When operating at clock
rates above 500MHz, differential input signals are
recommended. For single-ended inputs, the V
BB
pin is tied
to the inverting differential input and bypassed via a 0.01碌F
capacitor. The V
BB
provides the switching reference for the
input differential amplifier. The V
BB
can also be used to AC
couple an input signal.
PIN CONFIGURATION
RESET
S
INA
S
INA
SYNC
MODE
NC
V
CCO
25 24 23 22 21 20 19
S
INB
S
INB
SEL
V
EE
CLK
CLK
V
BB
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
TOP VIEW
PLCC
J28-1
16
15
14
13
12
S
OUT
S
OUT
V
CC
Q
0
Q
1
V
CCO
Q
2
V
CCO
CL/4
PIN NAMES
Pin
SINA, SINA
SINB, SINB
SEL
SOUT, SOUT
Q0鈥換3
CLK, CLK
CL/4, CL/4
CL/8, CL/8
MODE
SYNC
RESET
V
CCO
Function
Differential Serial Data Input A
Differential Serial Data Input B
Serial Input Select Pin
Differential Serial Data Output
Parallel Data Outputs
Differential Clock Inputs
Differential
梅4
Clock Output
Differential
梅8
Clock Output
Conversion Mode 4-bit/8-bit
Conversion Synchronizing Input
Input, Resets the Counters
V
CC
to Output
V
CCO
Q
3
CL/8
CL/8
CL/4
Rev.: D
Amendment: /0
1
Issue Date: October, 1998
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