1500ps max. clock to bus
1000ps max. clock to Q
鈩?/div>
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E336
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E336 offer three bus transceivers with
both transmit and receive registers and are designed for
use in new, high-performance ECL systems. The bus
outputs (BUS
0
- BUS
2
) are designed to drive a 25鈩?bus.
The receive outputs (Q
0
鈥?Q
2
) are specified for 50鈩? The
bus outputs feature a normal logic HIGH level (V
OH
) and a
cutoff LOW level when at a logic LOW. At cutoff, the outputs
go to 鈥?.0V and the output emitter-follower is 鈥渙ff鈥?
presenting a high impedance to the bus. The bus outputs
have edge slow-down capacitors.
The Transmit Enable pins (TEN) determine whether
current data is held in the transmit register or new data is
loaded from the A/B inputs. A logic LOW on both of the bus
enable inputs (BUSEN), when clocked through the register,
disables the bus outputs to 鈥?.0V.
The receiver section clocks bus data into the receive
registers after gating with the Receive Enable (RXEN)
input.
All registers are clocked by rising edge of CLK
1
or CLK
2
(or both).
Additional grounding is provided through the ground
pins (GND) which should be connected to 0V. The GND
pins are not electrically connected to the chip.
PIN CONFIGURATION
TEN
2
TEN
1
V
CCO
B
2
A
2
NC
Q
2
PIN NAMES
Pin
A
0
鈥揂
2
B
0
鈥揃
2
18
17
Function
Data Inputs A
Data Inputs B
Transmit Enable Inputs
Receive Enable Input
Bus Enable Inputs
Clock Inputs
25鈩?Cutoff Bus Outputs
Receive Data Outputs
V
CC
to Output
25 24 23 22 21 20 19
BUSEN
1
BUSEN
2
RXEN
V
EE
CLK
1
CLK
2
A
0
26
27
28
1
2
3
4
5
6
7
8
9
10 11
TOP VIEW
PLCC
J28-1
16
15
14
13
12
GND
BUS
2
V
CC
Q
1
V
CCO
BUS
1
GND
TEN
1, 2
RXEN
BUSEN
1, 2
CLK
1, 2
BUS
0
鈥揃US
2
Q
0
鈥換
2
V
CCO
V
CCO
BUS
0
GND
Q
0
B
0
A
1
B
1
Rev.: C
Amendment: /2
1
Issue Date: February, 1998
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2
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