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SY10E196JC Datasheet

  • SY10E196JC

  • PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT

  • 82.59KB

  • 9頁

  • MICREL   MICREL

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PROGRAMMABLE DELAY
CHIP WITH ANALOG INPUT
ClockWorks鈩?/div>
SY10E196
SY100E196
FEATURES
s
Up to 2ns delay range
s
Extended 100E V
EE
range of 鈥?.2V to 鈥?.5V
s
鈮?/div>
20ps digital step resolution
s
Linear input for tighter resolution
s
>1GHz bandwidth
s
On-chip cascade circuitry
s
75Kk
鈩?/div>
input pulldown resistor
s
Fully compatible with Motorola MC10E/100E196
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E196 are programmable delay chips
(PDCs) designed primarily for very accurate differential
ECL input edge placement applications.
The delay section consists of a chain of gates and a
linear ramp delay adjustment organized as shown in the
logic diagram. The first two delay elements feature gates
that have been modified to have delays 1.25 and 1.5
times the basic gate delay of approximately 80ps. These
two elements provide the E196 with a digitally-selectable
resolution of approximately 20ps. The required device
delay is selected by the seven address inputs D[0:6],
which are latched on-chip by a high signal on the latch
enable (LEN) control. If the LEN signal is either LOW or
left floating, then the latch is transparent.
The FTUNE input takes an analog coltage and applies
it to an internal linear ramp for reducing the 20s resolution
still further. The FTUNE input is what differentiates the
E196 from the E195.
An eighth latched input, D7, is provided for cascading
multiple PDCs for increased programmable range. The
cascade logic allows full control of multiple PDCs, at the
expense of only a single added line to the data bus for
each additional PDC, without the need for any external
gating.
PIN CONFIGURATION
NC
18
17
25 24 23 22 21 20 19
D
1
D
0
LEN
V
EE
IN
IN
V
BB
26
27
28
1
2
3
4
5
6
7
8
9
10 11
D
6
D
7
D
2
D
3
D
4
D
5
TOP VIEW
PLCC
J28-1
16
15
14
13
12
FTUNE
NC
V
CC
V
CCO
Q
Q
V
CCO
PIN NAMES
Pin
IN/IN
Function
Signal Input
Input Enable
Mux Select Inputs
Signal Output
Latch Enable
Minimum Delay Set
Maximum Delay Set
Cascade Signal
Linear Voltage Input
V
CC
to Output
EN
SET MIN
SET MAX
CASCADE
NC
NC
CASCADE
EN
D[0:7]
Q/Q
LEN
SET MIN
SET MAX
CASCADE
FTUNE
V
CCO
Rev.: E
Amendment: /0
1
Issue Date: October, 1998

SY10E196JC 產(chǎn)品屬性

  • 38

  • 集成電路 (IC)

  • 時鐘/計(jì)時 - 延遲線

  • 10E, Precision Edge®

  • 7

  • 可編程

  • 1.39ns

  • 20ps

  • 1.39ns ~ 3.63ns

  • 1

  • -4.2 V ~ -5.5 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 28-LCC（J 形引線）

  • 28-PLCC

  • 管件

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