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SY10E193JC Datasheet

  • SY10E193JC

  • ERROR DETECTION/ CORRECTION CIRCUIT

  • 4頁

  • MICREL   MICREL

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ERROR DETECTION/
CORRECTION CIRCUIT
SY10E193
SY100E193
FEATURES
s
Hamming code generation
s
Extended 100E V
EE
range of 鈥?.2V to 鈥?.5V
s
8-bit wide
s
Expandable for more width
s
Provides parity register
s
Fully compatible with industry standard 10KH,
100K ECL levels
s
Internal75K
鈩?/div>
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E193
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E193 are error detection and correction
(EDAC) circuits designed for use in new, high- performance
ECL systems. The E193 generates hamming parity codes
on an 8-bit word as shown in the block diagram. The P
5
output gives the parity of the whole word. PGEN provides
word parity after Odd/Even parity control and gating with
the BPAR input. PGEN also feeds into a 1-bit shiftable
register for use as part of a scan ring.
The combinatorial part of the device generates the same
code pattern as the Motorola MC10193.
Used in conjunction with 12-bit parity generators, such
as the E160, a SECDED (single error correction, double
error detection) error system can be designed for a multiple
of an 8-bit word.
PIN CONFIGURATION
S-IN
SHIFT
EN
HOLD
V
CCO
PGEN
PIN NAMES
Pin
B
0
鈥揃
7
BPAR
Function
Check Bit Inputs
Check Bit Parity Input
Even/Odd Parity Select
Parity Enable
Syndrome Hold Input
Syndrome Bit Input
Syndrome Bit Shift
Clock Input
Parity Output
Parity Generate Output
Parity Error Output
V
CC
to Output
CLK
25 24 23 22 21 20 19
EV/OD
18
17
EV/OD
BPAR
B
0
V
EE
B
1
B
2
B
3
26
27
28
1
2
3
4
5
6
7
8
9
10 11
PARERR
PARERR
V
CC
P
5
V
CCO
P
4
P
3
EN
HOLD
S-IN
SHIFT
CLK
P
1
鈥揚
5
PGEN
PARERR/PARERR
V
CCO
TOP VIEW
PLCC
J28-1
16
15
14
13
12
V
CCO
P
1
P
2
B
4
B
5
B
6
B
7
Rev.: C
Amendment: /1
1
Issue Date: February, 1998

SY10E193JC 產(chǎn)品屬性

  • 38

  • 集成電路 (IC)

  • 邏輯 - 奇偶校驗發(fā)生器和校驗器

  • 10E

  • 奇偶發(fā)生器

  • 8 位

  • -

  • 4.2 V ~ 5.5 V

  • 0°C ~ 85°C

  • 表面貼裝

  • 28-LCC（J 形引線）

  • 28-PLCC

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