1000MHz min. operating frequency
800ps max. clock to output
鈩?/div>
input pulldown resistors
s
ESD protection of 2000V
s
Fully compatible with Motorola MC10E/100E167
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E167 offer six 2:1 multiplexers followed
by D flip-flops with single-ended outputs, designed for use
in new, high-performance ECL systems. The Select (SEL)
control allows one of the two data inputs to the multiplexer
to pass through. The two external clock signals (CLK
1
,
CLK
2
) are gated through a logical OR operation before use
as control for the six flip-flops. The selected data are
transferred to the flip-flops on the rising edge of CLK
1
or
CLK
2
(or both).
The multiplexer operation is controlled by the Select
(SEL) signal which selects one of the two bits of input data
at each mux to be passed through.
When a logic HIGH is applied to the Master Reset (MR)
signal, it operates asychronously to take all outputs Q to a
logic LOW.
BLOCK DIAGRAM
D
0a
MUX
D
0b
D
1a
MUX
D
1b
D
2a
MUX
D
2b
D
3a
MUX
D
3b
D
4a
MUX
D
4b
D
5a
MUX
D
5b
SEL
CLK
1
CLK
2
MR
SEL
SEL
D
R
SEL
D
R
Q
Q
5
SEL
D
R
Q
Q
4
SEL
D
R
Q
Q
3
SEL
D
R
Q
Q
2
D
R
Q
Q
0
PIN CONFIGURATION
D
3b
D
3a
NC
V
CCO
D
5a
D
5b
CLK
1
CLK
2
V
EE
MR
SEL
D
0a
25 24 23 22 21 20 19
D
4b
D
4a
Q
Q
1
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
Q
5
Q
4
V
CC
Q
3
Q
2
V
CCO
Q
1
TOP VIEW
PLCC
J28-1
16
15
14
13
12
D
0b
D
1a
D
1b
PIN NAMES
Pin
D
0a
鈥揇
5a
D
0b
鈥揇
5b
SEL
CLK
1
, CLK
2
MR
Q
0
鈥換
5
V
CCO
Function
Input Data a
Input Data b
Select Input
Clock Inputs
Master Reset
Data Outputs
V
CC
to Output
Rev.: C
Amendment: /1
漏 1999 Micrel-Synergy
5-127
V
CCO
Q
0
Issue Date: February, 1998
D
2a
D
2b
1
2
3
