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SY100S863JC Datasheet

  • SY100S863JC

  • 8-INPUT PECL DIFFERENTIAL MUX WITH TTL SELECTS

  • 7頁

  • MICREL   MICREL

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8-INPUT PECL
DIFFERENTIAL MUX
WITH TTL SELECTS
FEATURES
s
Low skew
s
Differential PECL inputs
s
Differential cut-off PECL outputs capable of driving
25
鈩?/div>
load for driving data bus
s
Tri-state TTL output
s
TTL select and enable input
s
Internal 75K
鈩?/div>
PECL input pull-down resistors
s
PECL I/O fully compatible with industry standard
s
Available in 28-pin PLCC package
SY100S863
DESCRIPTION
The SY100S863 is a PECL 8:1 multiplexer designed for
use in new, high-performance PECL systems. It has
differential PECL outputs and a standard TTL output. The
TTL select inputs (SEL
0
, SEL
1
, SEL
2
) determine which one
of the eight differential PECL data inputs (D
0
鈥揇
7
) is
propagated to the outputs. The enable pin, EN, is provided
for expansion. When EN is at a TTL logic one level, both
PECL and TTL outputs are enabled. When the enable pin
is set to TTL logic zero level, both PECL outputs of the
differential pair are in cut-off and the TTL output is in a
three-state condition.
BLOCK DIAGRAM
D
0
(4)
D
0
(5)
D
1
(6)
D
1
(7)
D
2
(8)
D
2
(9)
D
3
(10)
D
3
(11)
D
4
(27)
D
4
(26)
D
5
(25)
D
5
(24)
D
6
(23)
D
6
(22)
D
7
(21)
D
7
(20)
EN (15)
PIN CONFIGURATION
D
7
V
CCO
D
5
D
5
D
6
25 24 23 22 21 20 19
D
4
D
6
D
7
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
16
Q
Q
V
CC
EN
V
CCT
Q
TTL
V
GT
8 DIFFERENTIAL
PECL INPUTS
(17) Q
(18) Q
8:1
MUX
(13) Q
TTL
D
4
SEL
0
V
EE
SEL
1
SEL
2
D
0
TOP VIEW
PLCC
J28-1
15
14
13
12
D
0
D
1
D
1
D
2
D
2
D
3
SEL
0
(28)
SEL
1
(2)
SEL
2
(3)
PIN NAMES
Pin
D
0
, /D
0
鈥?D
7
, /D
7
Q, /Q
Q
TTL
EN
SEL
0,1,2
Function
Differential PECL Input Pairs
Differential PECL Outputs
TTL Output
Enable Input
Select Inputs
TTL INPUTS
D
3
Rev.: E
Amendment: /0
1
Issue Date: May 2000

SY100S863JC 產(chǎn)品屬性

  • 38

  • 集成電路 (IC)

  • 邏輯 - 信號開關(guān)，多路復(fù)用器，解碼器

  • 100S

  • 多路復(fù)用器

  • 1 x 8:1

  • 1

  • -

  • 雙電源

  • -

  • 0°C ~ 85°C

  • 表面貼裝

  • 28-LCC（J 形引線）

  • 28-PLCC

  • 管件

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