鈩?/div>
input pull-down resistors
s
Available in 20-pin SOIC package
DESCRIPTION
The SY100S839V is a low skew
梅2/4, 梅4/5/6
clock
generation chip designed explicitly for low skew clock
generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The device can be driven
by either a differential or single-ended ECL/LVECL or, if
positive power supplies are used, PECL/LVPECL input
signal. In addition, by using the V
BB
output, a sinusoidal
source can be AC-coupled into the device. If a single-
ended input is to be used, the V
BB
output should be
connected to the /CLK input and bypassed to ground via
a 0.01碌F capacitor. The V
BB
output is designed to act as
the switching reference for the input of the S839V under
single-ended input conditions. As a result, this pin can
only source/sink up to 0.5mA of current.
The common enable (/EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the
negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a
random state; the master reset (MR) input must be
asserted to ensure synchronization. For systems which
only use one S839V, the MR pin need not be exercised
as the internal divider designs ensures synchronization
between the
梅2/4,
and the
梅4/5/6
outputs of a single
device.
PIN CONFIGURATION/BLOCK DIAGRAM
V
CC
20
Q
0
19
Q
0
18
Q
1
17
Q
1
16
Q
2
15
Q
2
14
Q
3
13
Q
3
12
V
EE
11
TOP VIEW
SOIC
Z20-1
1
V
CC
2
EN
3
4
CLK
5
CLK
6
V
BB
7
MR
8
V
CC
9
10
DIVSELb0
DIVSELb1
TRUTH TABLE
CLK
Z
ZZ
X
/EN
L
H
X
MR
L
L
H
Function
Divide
Hold Q
0鈥?
Reset Q
0鈥?
NOTE:
Z = LOW-to-HIGH transition
ZZ = HIGH-to-LOW transition
DIVSELa
PIN NAMES
Q
0,
Q
1
OUTPUTS
Divide by 2
Divide by 4
Pin
CLK
/EN
Function
Differential Clock Inputs
Synchronous Enable
Master Reset
Reference Output
Differential
梅2/4
Outputs
Differential
梅4/5/6
Outputs
Frequency Select Input
Rev.: A
Amendment: /0
DIVSELa
0
1
DIVSELb1
0
0
1
1
DIVSELb0
0
1
0
1
Q
2,
Q
3
OUTPUTS
Divide by 4
Divide by 6
Divide by 5
Divide by 5
MR
V
BB
Q
0,
Q
1
Q
2,
Q
3
DIVSEL
1
Issue Date: May, 1999
MICREL
1
2
3
4
5
