Max. propagation delay of 1000ps
min. of 鈥?8mA
鈩?/div>
input pull-down resistors
s
40% faster than Fairchild
s
40% lower power than Fairchild
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
S
0
S
1
V
EE
V
EES
E
12
13
14
15
16
17
18
Top View
PLCC
J28-1
SY100S371
DESCRIPTION
The SY100S371 is an ultra-fast triple 4-input multiplexer
with true and complementary outputs designed for use in
high-performance ECL systems. The multiplexer is
controlled by common select inputs S
0
and S
1
. A logic
HIGH on the Enable (E) control input takes the outputs to
a logic LOW. The inputs on the device have 75K鈩?pull-
down resistors.
PIN CONFIGURATIONS
I
2a
I
1a
V
EES
I
3a
I
0a
Z
a
Z
a
11 10 9 8 7 6 5
4
3
2
1
28
27
26
Z
b
Z
b
V
CCA
V
CC
V
CC
Z
c
Z
c
BLOCK DIAGRAM
S
0
S
1
I
0a
I
1a
I
2a
I
3a
I
0b
I
1b
I
2b
I
3b
I
0c
I
1c
I
2c
I
3c
E
Z
c
Z
c
Z
b
Z
b
Z
a
Z
a
I
0b
I
1b
19 20 21 22 23 24 25
I
3b
I
0c
I
2b
V
EES
I
1c
I
2c
I
3c
I
0b
E
V
EE
I
1b
S
1
I
2b
I
3b
I
0c
I
1c
I
2c
I
3c
1
2
3
4
5
6
24 23 22 21 20 19
18
Top View
Flatpack
F24-1
17
16
15
14
S
0
I
3a
I
2a
I
1a
I
0a
Z
a
Z
a
13
7 8 9 10 11 12
Z
c
V
CC
Z
c
V
CCA
Z
b
Z
b
Rev.: G
Amendment: /0
1
Issue Date: July, 1999