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SY100S360JCTR Datasheet

  • SY100S360JCTR

  • DUAL PARITY CHECKER/ GENERATOR

  • 5頁(yè)

  • MICREL   MICREL

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DUAL PARITY
CHECKER/
GENERATOR
FEATURES
s
Max. propagation delay of 2200ps
s
I
EE
min. of 鈥?0mA
s
Industry standard 100K ECL levels
s
Extended supply voltage option:
V
EE
= 鈥?.2V to 鈥?.5V
s
Voltage and temperature compensation for improved
noise immunity
s
Internal 75K
鈩?/div>
input pull-down resistors
s
15% faster than Fairchild 300K
s
Approximately 30% lower power than Fairchild 300K
s
Function and pinout compatible with Fairchild F100K
I
4a
I
3a
V
EES
SY100S360
DESCRIPTION
The SY100S360 is a dual parity checker/generator and
is designed for use in high-performance ECL systems. The
inputs are segmented into two groups of nine inputs each
and the parity output is at a logic LOW when an even
number of inputs are at a logic HIGH. In each group, one of
the nine inputs (Ia, Ib) has a shorter propagation delay and,
therefore, is ideal as the expansion input for parity
generation of wider data.
A Compare output (C) is also provided which allows
comparison of two 8-bit words. A logic LOW on the C output
indicates a match. The inputs on this device have 75K鈩?/div>
pull-down resistors.
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
PIN CONFIGURATIONS
I
5a
I
2a
I
1a
I
0a
11 10 9 8 7 6 5
BLOCK DIAGRAM
I
0a
I
1a
I
2a
I
3a
I
4a
I
5a
I
6a
I
7a
I
a
C
I
0b
I
1b
I
2b
I
3b
I
4b
I
5b
I
6b
I
7b
I
b
Z
b
Z
a
I
6a
I
7a
V
EE
V
EES
I
0b
I
1b
I
2b
12
13
14
15
16
17
18
Top View
PLCC
J28-1
4
3
2
1
28
27
26
I
a
Z
a
V
CCA
V
CC
V
CC
C
Z
b
19 20 21 22 23 24 25
I
1b
I
0b
V
EE
I
2b
I
7a
V
EES
I
6b
I
7b
I
b
I
3b
I
4b
I
5b
I
3b
I
4b
I
5b
I
6b
I
7b
I
b
24 23 22 21 20 19
1
18
2
3
4
5
6
Top View
Flatpack
F24-1
17
16
15
14
I
6a
I
5a
I
4a
I
3a
I
2a
I
1a
I
0a
13
7 8 9 10 11 12
C
V
CC
V
CCA
Z
b
Rev.: G
Z
a
I
a
Amendment: /0
1
Issue Date: July, 1999

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