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SY100S351JCTR Datasheet

  • SY100S351JCTR

  • HEX D FLIP-FLOP

  • 114.21KB

  • 7頁

  • MICREL   MICREL

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HEX D FLIP-FLOP
SY100S351
FEATURES
s
Max. toggle frequency of 700MHz
s
Clock to Q max. of 1200ps
s
I
EE
min. of 鈥?8mA
s
Industry standard 100K ECL levels
s
Extended supply voltage option:
V
EE
= 鈥?.2V to 鈥?.5V
s
Voltage and temperature compensation for improved
noise immunity
s
Internal 75K
鈩?/div>
input pull-down resistors
s
50% faster than Fairchild 300K
s
Better than 20% lower power than Fairchild
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
DESCRIPTION
The SY100S351 offers six D-type, edge-triggered,
master/slave flip-flops with differential outputs, and is
designed for use in high-performance ECL systems. The
flip-flops are controlled by the signal from the logical OR
operation on a pair of common clock signals (CP
a
, CP
b
).
Data enters the master when both CP
a
and CP
b
are LOW
and transfers to the slave when either CP
a
or CP
b
(or both)
go to a logic HIGH. The Master Reset (MR) input overrides
all other inputs and takes the Q outputs to a logic LOW. The
inputs on this device have 75K鈩?pull-down resistors.
PIN CONFIGURATIONS
D
0
Q
0
V
EES
Q
0
Q
1
Q
1
4
3
2
1
28
27
26
19 20 21 22 23 24 25
11 10 9 8 7 6 5
D
2
D
3
V
EE
V
EES
MR
12
13
14
15
16
17
18
Q
2
Q
2
V
CCA
V
CC
V
CC
Q
3
Q
3
D
1
CP
a
CP
b
Top View
PLCC
J28-1
BLOCK DIAGRAM
D
5
CP
b
CP
a
MR
D
4
D
E
R
Q
Q
Q
5
CP
b
CP
a
MR
V
EE
D
3
Q
5
Q
4
Q
5
V
EES
D
E
R
Q
Q
Q
4
Q
4
D
4
D
5
Q
5
Q
5
Q
4
Q
4
24 23 22 21 20 19
1
18
2
3
4
5
6
Top View
Flatpack
F24-1
17
16
15
14
D
2
D
5
Q
5
D
4
Q
4
D
1
D
0
Q
0
Q
0
Q
1
Q
1
D
3
D
E
R
Q
Q
Q
3
Q
3
13
7 8 9 10 11 12
Q
3
V
CC
Q
3
D
2
D
E
R
Q
Q
Q
2
Q
2
D
1
D
E
Q
R Q
Q
R Q
Q
1
Q
1
D
0
D
E
Q
0
Q
0
Rev.: G
V
CCA
Q
2
Q
2
Amendment: /0
1
Issue Date: July, 1999

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