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SY100S324JCTR Datasheet

  • SY100S324JCTR

  • LOW POWER HEX TTL-to-ECL TRANSLATOR

  • 5頁

  • MICREL   MICREL

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LOW POWER HEX
TTL-to-ECL
TRANSLATOR
FEATURES
s
Max. propagation delay of 1.4ns
s
I
EE
min. of 鈥?0mA
s
Industry standard 100K ECL levels
s
Extended supply voltage option:
V
EE
= 鈥?.2V to 鈥?.5V
s
Differential outputs
s
Voltage and temperature compensation for improved
noise immunity
s
Internal 75K
鈩?/div>
input pull-down resistors
s
Twice as fast as Fairchild鈥檚 324
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
SY100S324
DESCRIPTION
The SY100S324 is a hex translator designed to convert
TTL logic levels to 100K ECL levels. The inputs are TTL
compatible with differential outputs that can either be
used as an inverting/non-inverting translator or as
differential line drivers. A common Enable (E), when LOW,
holds all inverting outputs HIGH and holds all non-
inverting outputs LOW.
When used in the differential mode, due to its high
common mode rejection, it overcomes voltage gradients
between the TTL and ECL ground systems. The V
EE
and
V
TTL
power may be applied in either order.
PIN CONFIGURATIONS
Q
0
V
EES
Q
1
Q
1
Q
0
D
2
D
1
25 24 23 22 21 20 19
BLOCK DIAGRAM
E
D
0
D
1
D
2
D
3
D
4
D
5
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
Q
4
Q
4
Q
5
Q
5
Q
2
Q
2
V
CC
V
CC
V
CCA
V
CCA
Q
3
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
16
D
0
V
TTL
E
V
EES
V
EE
D
3
D
4
V
TTL
V
EE
Top View
PLCC
J28-1
15
14
13
12
D
0
V
EES
Q
5
Q
5
Q
3
Q
4
Q
4
D
5
24
23
22
21
D
1
D
2
Q
0
Q
0
Q
1
Q
1
D
3
E
20 19
18
17
D
4
1
2
3
4
5
6
7
8
9
10
11
12
D
5
Q
5
Q
5
Q
4
Q
4
Q
3
Top View
Flatpack
F24-1
16
15
14
13
V
CC
Q
2
Q
2
V
CCA
PIN NAMES
Pin
D
0
鈥揇
5
E
Q
0
鈥換
5
Q
0
鈥換
5
V
EES
V
TTL
V
CCA
Data Inputs
Enable Inputs
Data Outputs
Complementary Data Outputs
V
EE
Substrate
TTL V
CC
Power Supply
V
CCO
for ECL Outputs
Rev.: F
Amendment: /0
Function
1
Issue Date: July, 1999
V
CCA
Q
3

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