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SY100S313JCTR Datasheet

  • SY100S313JCTR

  • QUAD DRIVER

  • 100.47KB

  • 5頁

  • MICREL   MICREL

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QUAD DRIVER
SY100S313
FEATURES
s
Max. propagation delay of 800ps
s
Enable to Output max. of 950ps
s
I
EE
min. of 鈥?0mA
s
Extended supply voltage option:
V
EE
= 鈥?.2V to 鈥?.5V
s
Voltage and temperature compensation for
improved noise immunity
s
Internal 75K
鈩?/div>
input pull-down resistors
s
50% faster than Fairchild 300K
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
DESCRIPTION
The SY100S313 offers four drivers with two OR and two
NOR outputs, designed for use in high-performance ECL
systems. The four drivers are controlled by a common
Enable signal which is buffered to minimize input loading.
If the D inputs are not used, the Enable signal can be used
to drive sixteen 50鈩?lines. All inputs have 75K鈩?pulldown
resistors and all outputs are buffered.
PIN CONFIGURATIONS
O
2a
O
a
V
EES
O
1a
O
2a
O
2b
O
1b
11 10 9 8 7 6 5
D
a
D
b
V
EE
V
EES
12
13
14
15
16
17
18
19 20 21 22 23 24 25
V
EES
O
2d
O
2c
O
2d
O
1d
O
1c
o
1d
4
3
Top View
PLCC
J28-1
2
1
28
27
26
O
2b
O
1b
V
CCA
V
CC
V
CC
O
1c
O
2c
BLOCK DIAGRAM
O
1a
O
2a
O
1a
O
2a
O
1b
O
2b
O
1b
O
2b
D
c
O
1c
O
2c
O
1c
O
2c
D
d
E
O
1d
O
2d
O
1d
O
2d
E
D
c
D
d
V
EE
D
b
D
d
D
b
O
1d
O
2d
O
1d
O
2d
O
2c
O
1c
1
2
3
4
5
6
24 23 22 21 20 19
18
Top View
Flatpack
F24-1
17
16
15
14
D
a
D
c
E
D
a
O
1a
O
2a
O
1a
O
2a
O
2b
O
1b
13
7 8 9 10 11 12
O
2c
O
1c
V
CC
V
CCA
PIN NAMES
Pin
D
a
鈥?D
d
E
O
na
鈥?O
nd
O
na
鈥?O
nd
V
EES
V
CCA
Function
Data Inputs (n-1...5)
Enable Input
Data Outputs
Complementary Data Outputs
V
EE
Substrate
V
CCO
for ECL Outputs
Rev.: G
Amendment: /0
1
Issue Date: July, 1999
O
1b
O
2b

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