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SY100EPT21LZCTR Datasheet

  • SY100EPT21LZCTR

  • 3.3V DIFFERENTIAL LVPECL-to-LVTTL TRANSLATOR

  • 8頁(yè)

  • MICREL   MICREL

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3.3V DIFFERENTIAL
LVPECL-to-LVTTL
TRANSLATOR
FEATURES
s
3.3V power supply
s
1.9ns typical propagation delay
s
275MHz f
MAX
(Clock bit stream, not pseudo-random)
s
Differential LVPECL inputs
s
24mA LVTTL outputs
s
Flow-through pinouts
s
Internal input resistors: pulldown on D, pulldown
and pullup on /D
s
Q output will default LOW with inputs open or at
GND
s
V
BB
output
s
Available in 8-pin MSOP and SOIC package
SY100EPT21L
DESCRIPTION
The SY100EPT21L is a single differential LVPECL-to-
LVTTL translator using a single +3.3V power supply.
Because LVPECL (Low Voltage Positive ECL) levels are
used, only +3.3V and ground are required. The small
outline 8-lead SOIC package and low skew single gate
design make the EPT21L ideal for applications that
require the translation of a clock or data signal where
minimal space, low power, and low cost are critical.
V
BB
allows a differential, single-ended, or AC-coupled
interface to the device. If used, the V
BB
output should be
bypassed to V
CC
with 0.01碌F capacitor.
Under open input conditions, the /D will be biased at a
V
CC
/2 voltage level and the D input will be pulled to
ground. This condition will force the Q output low to
provide added stability.
The 100EPT is compatible with positive ECL 100K
logic levels.
PIN CONFIGURATION/BLOCK DIAGRAM
PIN NAMES
Pin
Function
LVTTL Output
Differential LVPECL Input Pair
Positive Supply
Output Reference Voltage
Ground
NC 1
D 2
LVPECL
LVTTL
8 V
CC
7 Q
6 NC
5 GND
Q
D, /D
V
CC
V
BB
GND
D 3
V
BB
4
(Available in 8-pin SOIC and 8-pin MSOP)
Rev.: A
Amendment: /1
1
Issue Date: July 2000

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