ECL Pro鈩?/div>
DESCRIPTION
The SY100EP57V is a high-speed, low-skew, fully
differential PECL/ECL 4:1 multiplexer in a 20-pin TSSOP
package. This device is a pin-for-pin, plug-in replacement
to the MC10/100EP57DT. The signal-path inputs (D0:D3)
accept differential signals as low as 150mVpk-pk. All I/O
pins are 100K EP PECL/ECL logic compatible.
AC鈥損erformance is guaranteed over the industrial 鈥?0擄C
to +85擄C temperature range and 3.0V to 5.5V supply voltage
range. This device will operate in PECL/LVPECL or ECL/
LVECL mode. The SY100EP57 propagation delay is less
than 520ps, and the Select-to-valid output delay is less
than 575ps over temperature and voltage. For clock
applications, the high-speed design combined with an
extremely fast rise/fall time of less than 220ps produces a
toggle frequency as high as 3GHz (400mVpk-pk swing).
Two V
BB
output reference pins (approx equal to V
CC
鈥?.4V)
are available for AC鈥揷oupled or single-ended applications.
The SY100EP57V is part of Micrel鈥檚 high-speed, Precision
Edge timing and distribution family. For applications that
require a different I/O combination, consult the Micrel website
at
www.micrel.com
, and choose from a comprehensive
product line of high-speed, low skew fanout buffers,
translators, and clock dividers.
PIN CONFIGURATION/BLOCK DIAGRAM
VCC 1
D0 2
/D0 3
D1 4
/D1 5
4:1
D2 6
/D2 7
D3 8
/D3 9
VEE 10
20 VCC
19 SEL1
18 SEL0
17 VCC
16 Q
15 /Q
14 VCC
13 VBB1
12 VBB2
11 VEE
CROSS REFERENCE TABLE
Micrel Semiconductor
SY100EP57VK4I
SY100EP57VK4ITR
ON Semiconductor
MC100EP57DT
MC100EP57DTR2
20-pin TSSOP Package
ECL Pro is a trademark of Micrel, Inc.
Rev.: B
Amendment: /0
March 2003
1
Issue Date: