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SY100EP111UTITR Datasheet

  • SY100EP111UTITR

  • 2.5 V/ 3.3V 1:10 DIFFERENTIAL LVPECL /LVECL/HSTL CLOCK DRIVE...

  • 9頁

  • MICREL   MICREL

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Micrel
2.5V/3.3V 1:10 DIFFERENTIAL
LVPECL/LVECL/HSTL CLOCK DRIVER
Precision Edge鈩?/div>
SY100EP111U
Precision Edge鈩?/div>
SY100EP111U
FEATURES
s
2.5V and 3.3V power supply options
s
Guaranteed AC parameters over temperature:
鈥?f
MAX
= 3GHz
鈥?< 25ps output-to-output skew
鈥?< 250ps t
r
/ t
f
鈥?< 400ps propagation delay
s
Wide temperature range: 鈥?0
擄
C to +85
擄
C
s
Differential design
s
V
BB
output for single-ended input applications
s
Fully compatible with industry standard 100K I/O
levels
s
Available in 32-pin TQFP package
Precision Edge鈩?/div>
DESCRIPTION
The SY100EP111U is a high-speed, low skew 1-to-10
differential fanout buffer designed for clock distribution in
new, high-performance systems. The internal 2:1 mux
allows the input to select between two differential clock
sources.
The device is specifically designed for low skew. The
interconnect scheme and metal layout are carefully
optimized for minimal gate-to-gate skew within the device.
Wafer characterization and process control ensure
consistent distribution of propagation delay from lot to lot.
The V
BB
output is intended for use as a reference
voltage for single-ended reception of ECL signals to that
device only. When using V
BB
for this purpose, it is
recommended that V
BB
is decoupled to V
CC
via a 0.01碌F
capacitor.
BLOCK DIAGRAM
Q
0
/Q
0
Q
1
/Q
1
Q
2
/Q
2
Q
3
CLK0
V
EE
/CLK0
75k鈩?/div>
75k鈩?/div>
75k鈩?/div>
/Q
3
0
Q
4
/Q
4
Q
5
/Q
5
V
EE
75k鈩?/div>
V
EE
CLK1
V
CC
1
Q
6
/Q
6
Q
7
/Q
7
/CLK1
75k鈩?/div>
75k鈩?/div>
V
EE
CLK_SEL
V
CC
75k鈩?/div>
Q
8
/Q
8
V
BB
Q
9
/Q
9
V
EE
Precision Edge is a trademark of Micrel, Inc.
M9999-070104
hbwhelp@micrel.com or (408) 955-1690
Rev.: E
Amendment: /1
1
Issue Date: July 2004

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