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SY100ELT22LZCTR Datasheet

  • SY100ELT22LZCTR

  • 3.3V DUAL TTL-to-DIFFERENTIAL PECL TRANSLATOR

  • 4頁(yè)

  • MICREL   MICREL

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3.3V DUAL
TTL-to-DIFFERENTIAL
PECL TRANSLATOR
FEATURES
s
3.3V power supply
s
300ps typical propagation delay
s
<100ps output-to-output skew
s
Differential PECL outputs
s
PNP TTL inputs for minimal loading
s
Flow-through pinouts
s
Available in 8-pin SOIC package
SY10ELT22L
SY100ELT22L
DESCRIPTION
The SY10/100ELT22L are dual TTL-to-differential
PECL translators with +3.3V power supply. Because
PECL (Positive ECL) levels are used, only +3.3V and
ground are required. The small outline 8-lead SOIC
package and the low skew, dual gate design of the
ELT22L makes it ideal for applications which require the
tranlation of a clock and a data signal.
The ELT22L is available in both ECL standards: the
10ELT is compatible with positive ECL 10H logic levels,
while the 100ELT is compatible with positive ECL 100K
logic levels.
PIN CONFIGURATION/BLOCK DIAGRAM
PIN NAMES
Pin
Function
Differential PECL Outputs
TTL Inputs
+3.3V Supply
Ground
Q
0
Q
0
Q
1
Q
1
1
2
PECL
3
4
TTL
8
7
6
5
V
CC
D
0
D
1
GND
Q
n
D
n
V
CC
GND
SOIC
TOP VIEW
Rev.: H
Amendment: /0
1
Issue Date: March, 1999

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