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SY100ELT21LZCTR Datasheet

  • SY100ELT21LZCTR

  • 3.3V DIFFERENTIAL LVPECL-to-LVTTL TRANSLATOR

  • 4頁

  • MICREL   MICREL

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3.3V DIFFERENTIAL
LVPECL-to-LVTTL
TRANSLATOR
FEATURES
s
3.3V power supply
s
2.0ns typical propagation delay
s
Low power
s
Differential LVPECL inputs
s
24mA TTL outputs
s
Flow-through pinouts
s
Available in 8-pin SOIC package
ClockWorks鈩?/div>
SY10ELT21L
SY100ELT21L
DESCRIPTION
The SY10/100ELT21L are single differential LVPECL-
to-LVTTL translators using a single +3.3V power supply.
Because LVPECL (Low Voltage Positive ECL) levels are
used, only +3.3V and ground are required. The small
outline 8-lead SOIC package and low skew single gate
design make the ELT21L ideal for applications that require
the translation of a clock or data signal where minimal
space, low power, and low cost are critical.
V
BB
allows a differential, single-ended, or AC-coupled
interface to the device. If used, the V
BB
output should be
bypassed to V
CC
with 0.01碌F capacitor.
Under open input conditions, the /D will be biased at a
V
CC
/2 voltage level and the D input will be pulled to
ground. This condition will force the Q output low to
provide added stability.
The ELT21L is available in both ECL standards: the
10ELT is compatible with positive ECL 10H logic levels,
while the 100ELT is compatible with positive ECL 100K
logic levels.
PIN CONFIGURATION/BLOCK DIAGRAM
PIN NAMES
Pin
Function
TTL Output
Differential LVPECL Inputs
+3.3V Supply
Reference Output
Ground
NC 1
D 2
PECL
TTL
8 V
CC
7 Q
6 NC
5 GND
Q
D, /D
V
CC
V
BB
GND
D 3
V
BB
4
Rev.: B
Amendment: /0
1
Issue Date: April 2000

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