TRIPLE LVPECL-TO-PECL
OR PECL-TO-LVPECL
TRANSLATOR
FEATURES
s
5V and 3.3V power supplies required
s
Also, supports LVPECL-to-PECL translation
s
500ps propagation delays
s
Fully differential design
s
Differential line receiver capability
s
Application note
s
Available in 20-pin SOIC package
SY100EL92
DESCRIPTION
The SY100EL92 is a triple LVPECL-to-PECL or PECL-
to-LVPECL translator. The device receives standard PECL
signals and translates them to differential LVPECL output
signals (or vice versa). SY100EL92 can also be used as a
differential line receiver for PECL-to-PECL or LVPECL-to-
LVPECL signals. However, please note that for the latter
we will need two different power supplies. Please refer to
Function Table for more details.
V
BB
outputs are provided for interfacing single ended
input signals. If a single ended input is to be used, the V
BB
output should be connected to the D input and the active
signal will drive the D input. When used, the V
BB
should be
bypassed to V
CC
via a 0.01碌F capacitor. The V
BB
is
designed to act as a switching reference for the SY100EL92
under single ended input conditions. As a result, the pin
can only source/sink 0.5mA of current.
To accomplish the PECL-to-LVPECL level translation,
the SY100EL92 requires three power rails. The V
CC
and
V
CC
_V
BB
supply is to be connected to the standard PECL
supply, the 3.3V supply is to be connected to the V
CCO
supply, and GND is connected to the system ground plane.
Both the V
CC
and V
CCO
should be bypassed to ground with
a 0.01碌F capacitor.
To accomplish the LVPECL-to-PECL level translation,
the SY100EL92 requires three power rails as well. The 5.0V
supply is connected to the V
CC
and V
CCO
pins, 3.3V supply
is connected to the V
CC
_V
BB
pin and GND is connected to
the system ground plane. V
CC
_V
BB
is used to provide a
proper V
BB
output level if a single ended input is used. For
differential LVPECL input V
CC
_V
BB
can be either 3.3V or
5V.
Under open input conditions, the D input will be biased
at a V
CC
/2 voltage level and the D input will be pulled to
GND. This condition will force the "Q" output low, ensuring
stability.
PIN CONFIGURATION/BLOCK DIAGRAM
V
CC_
V
BB
1
D
0
2
D
0
3
V
BB
4
20
V
CC
19
18
17
16
15
14
13
12
11
Q
0
Q
0
V
CCO
Q
1
Q
1
V
CCO
Q
2
Q
2
V
CC
D
1
5
D
1
6
V
BB
7
D
2
8
D
2
9
GND
10
SOIC
TOP VIEW
FUNCTION TABLE
Function
PECL-to-LVPECL
LVPECL-to-PECL
PECL-to-PECL
LVPECL-to-LVPECL
Vcc
5.0V
5.0V
5.0V
5.0V
Vcco
3.3V
5.0V
5.0V
3.3V
Vcc_V
BB
5.0V
3.3V
5.0V
3.3V
PIN NAMES
Pin
Dn
Q
n
V
BB
V
CCO
V
CC
_V
BB
GND
V
CC
Function
PECL / LVPECL Inputs
PECL / LVPECL Outputs
PECL / LVPECL Reference Voltage Output
V
CC
for Output
V
CC
for V
BB
Output
Common Ground Rail
V
CC
for Internal Circuitry
Rev.: D
Amendment: /0
1
Issue Date: January, 1999
MICREL
1
2
3
4
