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SY100EL91LZCTR Datasheet

  • SY100EL91LZCTR

  • 3.3V TRIPLE LVPECL-to-ECL OR LVPECL-to-LVECL TRANSLATOR

  • 5頁

  • MICREL   MICREL

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3.3V TRIPLE LVPECL-to-ECL
OR LVPECL-to-LVECL
TRANSLATOR
FEATURES
s
3.3V power supply
s
620ps propagation delay
s
Fully differential design
s
Supports low voltage operation
s
Available in 20-pin SOIC package
SY100EL91L
DESCRIPTION
The SY100EL91L is a triple LVPECL-to-ECL or
LVPECL-to-LVECL translator.
A V
BB
output is provided for interfacing with single
ended PECL signals at the input. If a single ended input
is to be used, the V
BB
output should be connected to the
D input. The active signal would then drive the D input.
When used, the V
BB
output should be bypassed to ground
via a 0.01碌F capacitor. The V
BB
output is designed to act
as the switching reference for the EL91L under single
ended input switching conditions. As a result this pin can
only source/sink up to 0.5mA of current.
To accomplish the level translation the EL91L requires
three power rails. The V
CC
supply should be connected
to the positive supply, and the V
EE
pin should be
connected to the negative power supply. The GND pins
as expected are connected to the system ground plane.
Both V
EE
and V
CC
should be bypassed to ground via
0.01碌F capacitors.
Under open input conditions, the D input will be biased
at V
CC
/2 and the D input will be pulled to GND. This
condition will force the Q output to a LOW, ensuring
stability.
PIN CONFIGURATION/BLOCK DIAGRAM
V
CC
1
D
0
2
D
0
3
20
V
CC
19
18
ECL
PECL
Q
0
Q
0
GND
Q
1
Q
1
GND
ECL
PECL_V
BB
4
D
1
5
D
1
6
PECL_V
BB
D
2
D
2
7
8
9
PECL
PECL
17
16
15
14
13
12
11
ECL
PIN NAMES
Q
2
Q
2
Pin
Dn
PECL Inputs
ECL Outputs
Q
n
PECL_V
BB
Function
V
EE
10
V
CC
PECL Reference Voltage Output
SOIC
TOP VIEW
FUNCTION TABLE
Function
LVPECL-to-ECL
LVPECL-to-LVECL
Vcc
3.3V
3.3V
V
EE
鈥?.0V
鈥?.3V
Rev.: F
Amendment: /2
1
Issue Date: November, 1999

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