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SY100EL57ZCTR Datasheet

  • SY100EL57ZCTR

  • 4:1 DIFFERENTIAL MULTIPLEXER

  • 4頁(yè)

  • MICREL   MICREL

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4:1 DIFFERENTIAL
MULTIPLEXER
SY10EL57
SY100EL57
FINAL
FEATURES
s
Useful as either 4:1 or 2:1 multiplexer
s
V
BB
output for single-ended operation
s
75K
鈩?/div>
internal input pulldown resistors
s
Available in 150 mil 16-pin SOIC package
DESCRIPTION
The SY10/100EL57 are fully differential 4:1 multiplexers.
By leaving the SEL1 line open (pulled LOW via the input
pulldown resistors) the device can also be used as a
differential 2:1 multiplexer with SEL0 input selecting between
D0 and D1. The fully differential architecture of the EL57
makes it ideal for use in low skew applications such as
clock distribution.
The SEL1 is the most significant select line. The binary
number applied to the select inputs will select the same
numbered data input (i.e., 00 selects D0).
Multiple V
BB
outputs are provided for single-ended or
AC coupled interfaces. In these scenarios, the V
BB
output
should be connected to the data bar inputs and bypassed
via a 0.01碌F capacitor to ground. Note that the V
BB
output
can source/sink up to 0.5mA of current without upsetting
the voltage level.
PIN CONFIGURATION/BLOCK DIAGRAM
V
CC
16
SEL0
15
SEL1
14
Q
13
Q
12
V
BB1
11
V
BB2
10
V
EE
9
4:1
1
2
3
4
5
6
7
8
D0
D0
D1
D1
D2
D2
D3
D3
SOIC
TOP VIEW
TRUTH TABLE
SEL1
L
L
H
H
SEL0
L
H
L
H
DATA OUT
D
0
D
1
D
2
D
3
PIN NAMES
Pin
D
0-3
SEL
0, 1
V
BB
1, 2
Q
Function
Differential Data Inputs
Mux Select Inputs
Reference Outputs
Data Outputs
Rev.: F
Amendment: /0
1
Issue Date: February 2003

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