1100MHz min. toggle frequency
ClockWorks鈩?/div>
SY100EL29V
DESCRIPTION
The SY100EL29V is a dual differential register with
differential data (inputs and outputs) and clock. The
registers are triggered by a positive transition of the
positive clock (CLK) input. A HIGH on the Reset (R
x
)
asynchronously resets the appropriate register so that
the Q outputs go LOW. A HIGH on the Set (S
x
)
asynchronously resets the appropriate register so that
the Q outputs go HIGH. The Set and Reset inputs cannot
both be HIGH simultaneously.
The differential input structures are clamped so that
the inputs of unused registers can be left open without
upsetting the bias network of the devices. The clamping
action will assert the /D and the /CLK sides of the inputs.
The noninverting input will pull down to V
EE
and the
inverting input will be biased around V
CC
/2. Because of
the edge-triggered flip-flop nature of the devices,
simultaneously opening both the clock and data inputs
will result in an output which reaches an unidentified but
valid state.
The fully differential design of the devices makes them
ideal for very high frequency applications where a
registered data path is necessary.
PIN CONFIGURATION/BLOCK DIAGRAM
R0 VCC Q0
20 19 18
Q
R
D
Q
S
CLK
Q0
17
S0
16
S1 VCC Q1
15 14 13
Q
S
D
Q
R
CLK
Q1 V
EE
12 11
1
D0
2
3
4
5
6
7
8
9
10
D0 CLK0 CLK0 VBB D1
D1 CLK1 CLK1 R1
SOIC
TOP VIEW
PIN NAMES
Pin
CLK, /CLK
D[0:1], /D[0:1]
Q[0:1], /Q[0:1]
R
0
, R
1
S
0
, S
1
V
BB
V
CC
V
EE
Function
Differential Clock Inputs
Differential Data Inputs
Differential Data Outputs
Reset Inputs
Set Inputs
V
BB
Reference Output
V
CC
V
EE
TRUTH TABLE
R
L
L
H
L
H
S
L
L
L
H
H
D
L
H
X
X
X
CLK
Z
Z
X
X
X
Q
L
H
L
H
Undef
/Q
H
L
H
L
Undef
NOTE:
Z = LOW-to-HIGH Transition
Rev.: B
Amendment: /0
1
Issue Date: February 2000
MICREL
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