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SY100EL14VZCTR Datasheet

  • SY100EL14VZCTR

  • 5V/3.3V 1:5 CLOCK DISTRIBUTION

  • 70.51KB

  • 4頁

  • MICREL   MICREL

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5V/3.3V 1:5 CLOCK
DISTRIBUTION
FEATURES
s
3.3V and 5V power supply options
s
Typical 30ps output-to-output skew
s
Max. 50ps output-to-output skew
s
Synchronous enable/disable
s
Multiplexed clock input
s
75K
鈩?/div>
internal input pull-down resistors
s
Available in 20-pin SOIC package
ClockWorks鈩?/div>
SY100EL14V
DESCRIPTION
The SY100EL14V is a low skew 1:5 clock distribution
chip designed explicitly for low skew clock distribution
applications. The device can be driven by either a
differential or single-ended ECL or, if positive power
supplies are used, PECL input signal. The EL14V is
suitable for operation in systems operating from 3.3V to
5.0V supplies. If a single-ended input is to be used the
V
BB
output should be connected to the CLK input and
bypassed to ground via a 0.01碌F capacitor. The V
BB
output is designed to act as the switching reference for
the input of the EL14V under single-ended input
conditions, as a result this pin can only source/sink up to
0.5mA of current.
The EL14V features a multiplexed clock input to allow
for the distribution of a lower speed scan or test clock
along with the high speed system clock. When LOW (or
left open and pulled LOW by the input pull-down resistor)
the SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the
outputs will only be enabled/disabled when they are
already in the LOW state. This avoids any chance of
generating a runt clock pulse when the device is enabled/
disabled as can happen with an asynchronous control.
The internal flip flop is clocked on the falling edge of the
input clock, therefore all associated specification limits
are referenced to the negative edge of the clock input.
When both differential inputs are left open, CLK input
will pull down to V
EE
and CLK input will bias around
V
CC
/2.
PIN CONFIGURATION/BLOCK DIAGRAM
V
CC
EN VCC NC SCLK CLK CLK V
BB
SEL V
EE
20 19 18 17 16 15 14 13 12 11
D
Q
1
0
1
Q0
2
Q0
3
Q1
4
Q1
5
Q2
6
Q2
7
Q3
8
Q3
9
Q4
10
Q4
SOIC
TOP VIEW
PIN NAMES
Pin
CLK
SCLK
EN
SEL
V
BB
Q
0-4
Function
Differential Clock Inputs
Scan Clock Input
Synchronous Enable
Clock Select Input
Reference Output
Differential Clock Outputs
TRUTH TABLE
CLK
L
H
X
X
X
SCLK
X
X
L
H
X
SEL
L
L
H
H
X
EN
L
L
L
L
H
Q
L
H
L
H
L*
* On next negative transition of CLK or SCLK
Rev.: A
Amendment: /0
1
Issue Date: October 1999

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