1.8GHz min. count frequency
鈩?/div>
input pull-down resistors
s
Available in 28-pin PLCC packge
DESCRIPTION
The SY10/100E137 are very high speed binary ripple
counters. The two least significant bits were designed
with very fast edge rates, while the more significant bits
maintain standard ECLinPS output edge rates. This allows
the counters to operate at very high frequencies, while
maintaining a moderate power dissipation level.
The devices are ideally suited for multiple frequency
clock generation, as well as for counters in high-
performance ATE time measurement boards.
Both asynchronous and synchronous enables are
available to maximize the device's flexibility for various
applications. The asynchronous enable input, A_Start,
when asserted, enables the counter while overriding any
synchronous enable signals. The E137 features XOR'ed
enable inputs, EN
1
and EN
2
, which are synchronous to
the CLK input. When only one synchronous enable is
asserted, the counter becomes disabled on the next CLK
transition. All outputs remain in the previous state poised
for the other synchronous enable or A_Start to be
asserted in order to re-enable the counter. Asserting
both synchronous enables causes the counter to become
enabled on the next transition of the CLK. EN
1
(or EN
2
)
and CLK edges are coincident. Sufficient delay has been
inserted in the CLK path (to compensate for the XOR
gate delay and the internal D-flip-flop set-up time) to
ensure that the synchronous enable signal is clocked
correctly; hence, the counter is disabled.
The E137 can also be driven single-endedly utilizing
the V
BB
output supply as the voltage reference for the
CLK input signal. If a single-ended signal is to be used,
the V
BB
pin should be connected to the CLK input and
bypassed to ground via a 0.01碌F capacitor. V
BB
can
only source/sink 0.5mA; therefore, it should be used as
a switching reference for the E137 only.
All input pins left open will be pulled LOW via an input
pull-down resistor. Therefore, do not leave the differential
CLK inputs open. Doing so causes the current source
transistor of the input clock gate to become saturated,
thus upsetting the internal bias regulators and
jeopardizing the stability of the device.
The asynchronous Master Reset resets the counter to
an all zero state upon assertion.
PIN CONFIGURATION
V
CCO
Q
6
Q
7
Q
7
Q
6
25 24 23 22
21 20 19
18
17
A_Start
EN
1
EN
2
V
EE
CLK
CLK
V
BB
Q
5
Q
5
26
27
28
1
2
3
4
5
6
7
8
9
10 11
Q
4
Q
4
V
CC
Q
3
Q
3
Q
2
Q
2
PLCC
TOP VIEW
J28-1
16
15
14
13
12
Q
0
Q
1
Q
0
V
CCO
MR
Q
1
PIN NAMES
Pin
CLK, CLK
Q
0
鈥換
7
, Q
0
鈥換
7
A_Start
EN
1
, EN
2
MR
V
BB
V
CCO
Function
Differential Clock Inputs
Differential Q Outputs
Asynchronous Enable Input
Synchronous Enable Inputs
Asynchronous Master Reset
Switching Reference Output
V
CC
to Output
V
CCO
Rev.: C
Amendment: /1
1
Issue Date: February, 1998
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