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SUD50N02-04P Datasheet

  • SUD50N02-04P

  • N-Channel 20-V (D-S) 175C MOSFET

  • 179.02KB

  • 3頁

  • VISHAY   VISHAY

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SPICE Device Model SUD50N02-04P
Vishay Siliconix
N-Channel 20-V (D-S) 175擄C MOSFET
CHARACTERISTICS
鈥?/div>
N- and P-Channel Vertical DMOS
鈥?/div>
Macro Model (Subcircuit Model)
鈥?/div>
Level 3 MOS
鈥?/div>
Apply for both Linear and Switching Application
鈥?/div>
Accurate over the
鈭?5
to 125擄C Temperature Range
鈥?/div>
Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the
鈭?5
to 125擄C
temperature ranges under the pulsed 0 to 10V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to
model the gate charge characteristics while avoiding convergence
difficulties of the switched C
gd
model. All model parameter values
are optimized to provide a best fit to the measured electrical data
and are not intended as an exact physical interpretation of the
device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 72389
08-Jun-04
www.vishay.com
1

SUD50N02-04P 產(chǎn)品屬性

  • Vishay

  • MOSFET

  • N-Channel

  • 20 V

  • +/- 20 V

  • 34 A

  • 4.3 mOhms

  • Single

  • + 175 C

  • SMD/SMT

  • TO-252-3

  • Reel

  • 15 ns

  • - 55 C

  • 8.3 W

  • 20 ns

  • 2000

  • 50 ns

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