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STY34NB50F Datasheet

  • STY34NB50F

  • N - CHANNEL 500V - 0.11ohm - 34 A - Max247 PowerMESH MOSFET

  • 90.42KB

  • 8頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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廬
STY34NB50F
N - CHANNEL 500V - 0.11鈩?- 34 A - Max247
PowerMESH鈩?MOSFET
TYPE
STY34NB50F
s
s
s
s
s
s
s
V
DSS
500 V
R
DS(on)
< 0.14
鈩?/div>
I
D
34 A
TYPICAL R
DS(on)
= 0.11
鈩?/div>
EXTREMELY HIGH dv/dt CAPABILITY
鹵
30V GATE TO SOURCE VOLTAGE RATING
100% AVALANCHE TESTED
LOW INTRINSIC CAPACITANCE
GATE CHARGE MINIMIZED
REDUCED VOLTAGE SPREAD
1
2
3
DESCRIPTION
Using the latest high voltage MESH OVERLAY
鈩?/div>
process, STMicroelectronics has designed an ad-
vanced family of power MOSFETs with outstand-
ing performances. The new patent pending strip
layout coupled with the Company鈥檚 proprietary
edge termination structure, gives the lowest
RDS(on) per area, exceptional avalanche and
dv/dt capabilities and unrivalled gate charge and
switching characteristics.
APPLICATIONS
s
HIGH CURRENT, HIGH SPEED SWITCHING
s
SWITCH MODE POWER SUPPLY (SMPS)
s
DC-AC CONVERTER FOR WELDING
EQUIPMENT AND UNINTERRUPTABLE
POWER SUPPLY AND MOTOR DRIVE
ABSOLUTE MAXIMUM RATINGS
Symb ol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(
鈥?/div>
)
P
tot
dv/dt
(1)
T
s tg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain- gate Voltage (R
GS
= 20 k鈩?
G ate-source Voltage
Drain Current (continuous) at T
c
= 25
o
C
Drain Current (continuous) at T
c
= 100 C
Drain Current (pulsed)
T otal Dissipation at T
c
= 25
o
C
Derating F actor
Peak Diode Recovery voltage slope
Storage Temperature
Max. O perating Junction Temperature
o
Max247鈩?/div>
INTERNAL SCHEMATIC DIAGRAM
Value
500
500
鹵
30
34
21.4
136
450
3.61
4.5
-65 to 150
150
(
1
) I
SD
鈮?4
A, di/dt
鈮?/div>
200 A/碌s, V
DD
鈮?/div>
V
(BR)DSS
, T
j
鈮?/div>
T
JMAX
Un it
V
V
V
A
A
A
W
W/ C
V/ns
o
o
o
C
C
(鈥? Pulse width limited by safe operating area
December 1999
1/8

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