Using the latest high voltage MESH OVERLAY鈩?/div>
process, STMicroelectronics has designed an advanced
family
of
power
MOSFETs
with
outstanding
performances. The new patent pending strip layout
coupled with the Company鈥檚 proprietary edge termination
structure, gives the lowest RDS(on) per area,
exceptional avalanche and dv/dt capabilities and
unrivalled gate charge and switching characteristics.
2
1
3
Max247
鈩?/div>
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
s
HIGH CURRENT, HIGH SWITCHING SPEED
s
SWITCH MODE POWER SUPPLY (SMPS)
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(鈥?
P
tot
E
AS
(1)
dv/dt
(2)
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuos) at T
C
= 25擄C
Drain Current (continuos) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Derating Factor
Single Pulse Avalanche Energy
Peak Diode Recovery voltage slope
Storage Temperature
Operating Junction Temperature
Value
100
100
鹵 20
140
99
560
450
3
2900
5
-55 to 175
-55 to 175
Unit
V
V
V
A
A
A
W
W/擄C
mJ
V/ns
擄C
擄C
(鈥?
Pulse width limited by safe operating area.
August 2001
.
(1) Starting T
j
= 25
o
C, I
D
= 70A, V
DD
= 50V
(2) I
SD
鈮?40A,
di/dt
鈮?00A/碌s,
V
DD