(on) = 0.013鈩?/div>
EXCEPTIONAL dv/dt CAPABILITY
100% AVALANCHE TESTED
APPLICATION ORIENTED
CHARACTERIZATION
SURFACE-MOUNTING D
虜
PAK (TO-263)
POWER PACKAGE IN TUBE (NO SUFFIX) OR
IN TAPE & REEL (SUFFIX 鈥淭4鈥?
TO-247
D
虜
PAK
TO-263
(Suffix 鈥淭4鈥?
3
1
DESCRIPTION
This MOSFET series realized with STMicroelectronics
unique STripFET process has specifically been designed
to minimize input capacitance and gate charge. It is
therefore suitable as primary switch in advanced high-
efficiency, high-frequency isolated DC-DC converters for
Telecom and Computer applications. It is also intended
for any applications with low gate drive requirements.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
s
HIGH-EFFICIENCY DC-DC CONVERTERS
s
UPS AND MOTOR CONTROL
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
(*)
I
D
I
DM
(鈥?
P
tot
dv/dt
(1)
E
AS (2)
V
ISO
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuous) at T
C
= 25擄C
Drain Current (continuous) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Derating Factor
Peak Diode Recovery voltage slope
Single Pulse Avalanche Energy
Insulation Withstand Voltage (DC)
Storage Temperature
Operating Junction Temperature
Value
STB_P_W80NF12
STP80NF12FP
120
120
鹵 20
80
80(#)
60
60(#)
320
320(#)
300
45
2.0
0.3
10
700
------
2500
-55 to 175
Unit
V
V
V
A
A
A
W
W/擄C
V/ns
mJ
V
擄C
(鈥?
Pulse width limited by safe operating area.
(*) Limited by Package
(2) I
SD
鈮?5A,
di/dt
鈮?00A/碌s,
V
DD
鈮?/div>
V
(BR)DSS
, T
j
鈮?/div>
T
JMAX.
(#) Refer to SOA for the max allovable currente values on FP-type
due to thermal resistance value.
(1) Starting T
j
= 25
o
C, I
D
= 40A, V
DD
= 45V
March 2003
1/12
next