鈩?/div>
LOW THRESHOLD DRIVE
ULTRA LOW ON-RESISTANCE
ULTRA FAST SWITCHING
100% AVALANCHE TESTED
VERY LOW GATE CHARGE
LOW PROFILE, VERY LOW PARASITIC
INDUCTANCE PowerSO-10 PACKAGE
10
1
PowerSO-10
INTERNAL SCHEMATIC DIAGRAM
DESCRIPTION
The
STV160NF02LA
eration of Application Specific STMicroelectronics
well established STripFET鈩?process based on a
very unique strip layout design. The resulting
MOSFET shows unrivalled high packing density
with ultra low on-resistance and superior switching
charactestics. Process simplification also trans-
lates into improved manufacturing reproducibility.
This device is particularly suitable for high current,
low voltage switching application where efficiency
is crucial
APPLICATIONS
s
BUCK CONVERTERS IN HIGH
PERFORMANCE TELECOM AND VRMs DC-
DC CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
(**)
I
D
I
DM
(
q
)
P
TOT
E
AS
(1)
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuos) at T
C
= 25擄C
Drain Current (continuos) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Derating Factor
Single Pulse Avalanche Energy
Storage Temperature
Max. Operating Junction Temperature
CONNECTION DIAGRAM (TOP VIEW)
Value
20
20
鹵 15
160
113
640
210
1.4
330
鈥?5 to 175
175
Unit
V
V
V
A
A
A
W
W/擄C
mJ
擄C
擄C
(
q
) Pulse width limited by safe operating area
Note: Marking will be STV160NF02AL
December 2000
(1) V
DD
= 35V, I
D
= 45A, R
G
= 22鈩?/div>
,
L = 330碌H, Starting T
j
=25擄C
(**)Limited only maximum junction temperature allowed by
PowerSO-10
1/8
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