鈩⑩€?/div>
strip-
based process. The resulting transistor shows ex-
tremely high packing density for low on-resistance,
rugged avalance characteristics and less critical align-
ment steps therefore a remarkable manufacturing re-
producibility.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
s
DC-DC & DC-AC CONVERTERS
s
DC MOTOR CONTROL (DISK DRIVES, etc.)
s
SYNCHRONOUS RECTIFICATION
MARKING
s
STQ0
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
( )
P
TOT
dv/dt(1)
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuous) at T
C
= 25擄C
Drain Current (continuous) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Derating Factor
Peak Diode Recovery voltage slope
Storage Temperature
Max. Operating Junction Temperature
Value
100
100
鹵 20
1
0.6
4
1.6
0.013
20
鈥?55 to 150
(1) I
SD
鈮?A,
di/dt
鈮?50A/碌s,
V
DD
鈮?/div>
V
(BR)DSS
, T
j
鈮?/div>
T
JMAX.
Unit
V
V
V
A
A
A
W
W/擄C
V/ns
擄C
(
q
) Pulse width limited by safe operating area
September 2002
1/6
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