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STS8DNH3LL Datasheet

  • STS8DNH3LL

  • DUAL N-CHANNEL 30V - 0.018 OHM - 8A SO-8 LOW GATE CHARGE STr...

  • 226.26KB

  • 9頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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STS8DNH3LL
DUAL N-CHANNEL 30V - 0.018
鈩?/div>
- 8A SO-8
LOW GATE CHARGE STripFET鈩?III POWER MOSFET
TYPE
STS8DNH3LL
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
V
DSS
30 V
R
DS(on)
<0.022
鈩?/div>
I
D
8A
TYPICAL R
DS
(on) = 0.018
鈩?/div>
OPTIMAL R
DS
(on) x Qg TRADE-OFF @ 4.5V
CONDUCTION LOSSES REDUCED
SWITCHING LOSSES REDUCED
DESCRIPTION
This application specific MOSFET is the Third generation
of STMicroelectronis unique "Single Feature Size鈩?quot;
strip-based process. The resulting transistor shows the
best trade-off between on-resistance and gate charge.
When used as high and low side in buck regulators, it
gives the best performance in terms of both conduction
and switching losses. This is extremely important for
motherboards where fast switching and high efficiency
are of paramount importance.
SO-8
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
鈻?/div>
SPECIFICALLY DESIGNED AND OPTIMISED
FOR HIGH EFFICIENCY CPU CORE DC/DC
CONVERTERS FOR MOBILE PC
S
Ordering Information
SALES TYPE
STS8DNH3LL
MARKING
S8DNH3LL
PACKAGE
SO-8
PACKAGING
TAPE & REEL
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(
鈥?
P
tot
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k
鈩?/div>
)
Gate- source Voltage
Drain Current (continuous) at T
C
= 25擄C
Drain Current (continuous) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Value
30
30
鹵 16
8
5
32
2
Rev.0.2
Unit
V
V
V
A
A
A
W
(
鈥?
Pulse width limited by safe operating area.
June 2004
1/9

STS8DNH3LL 產(chǎn)品屬性

  • 1

  • 分離式半導(dǎo)體產(chǎn)品

  • FET - 陣列

  • STripFET™

  • 2 個 N 溝道（雙）

  • 邏輯電平門

  • 30V

  • 8A

  • 22 毫歐 @ 4A，10V

  • 1V @ 250µA

  • 10nC @ 4.5V

  • 857pF @ 25V

  • 2W

  • 表面貼裝

  • 8-SOIC（0.154"，3.90mm 寬）

  • 8-SO

  • Digi-Reel?

  • 497-8213-ND - BOARD EVAL ST7FMC2S4T6/STS8DNH3L

  • 497-4399-6

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