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STS8DNF3LL Datasheet

  • STS8DNF3LL

  • DUAL N-CHANNEL 30V - 0.017 ohm - 8A SO-8 LOW GATE CHARGE STr...

  • 8頁(yè)

  • STMICROELECTRONICS   STMICROELECTRONICS

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DUAL N-CHANNEL 30V - 0.017
鈩?/div>
- 8A SO-8
LOW GATE CHARGE STripFET鈩?II POWER MOSFET
TYPE
STS8DNF3LL
s
s
s
s
STS8DNF3LL
V
DSS
30 V
R
DS(on)
<0.020
鈩?/div>
I
D
8A
TYPICAL R
DS
(on) = 0.017鈩?/div>
OPTIMAL R
DS
(on) x Qg TRADE-OFF @ 4.5V
CONDUCTION LOSSES REDUCED
SWITCHING LOSSES REDUCED
DESCRIPTION
This application specific Power MOSFET is the second
generation of STMicroelectronis unique "Single Feature
Size鈩?quot; strip-based process. The resulting transistor
shows the best trade-off between on-resistance and gate
charge. When used as high and low side in buck
regulators, it gives the best performance in terms of both
conduction and switching losses. This is extremely
important for motherboards where fast switching and
high efficiency are of paramount importance.
SO-8
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
s
SPECIFICALLY DESIGNED AND OPTIMISED
FOR HIGH EFFICIENCY CPU CORE DC/DC
CONVERTERS FOR MOBILE PC
S
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuous) at T
C
= 25擄C
Single Operation
Drain Current (continuous) at T
C
= 100擄C
Single Operation
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C Dual operating
Total Dissipation at T
C
= 25擄C Single operating
Value
30
30
鹵 16
8
5
32
2
1.6
A
Unit
V
V
V
I
D
I
DM
(鈥?
P
tot
A
W
W
1/8
(鈥?
Pulse width limited by safe operating area.
October 2002
.

STS8DNF3LL 產(chǎn)品屬性

  • STS8DNF3LL View All Specifications

  • 1

  • 分離式半導(dǎo)體產(chǎn)品

  • FET - 陣列

  • STripFET™

  • 2 個(gè) N 溝道（雙）

  • 邏輯電平門

  • 30V

  • 8A

  • 20 毫歐 @ 4A，10V

  • 1V @ 250µA

  • 17nC @ 5V

  • 800pF @ 25V

  • 1.6W

  • 表面貼裝

  • 8-SOIC（0.154"，3.90mm 寬）

  • 8-SO

  • Digi-Reel?

  • 497-2470-6

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