鈩?/div>
STANDARD OUTLINE FOR EASY
AUTOMATED SURFACE MOUNT ASSEMBLY
ULTRA LOW GATE CHARGE
ULTRA LOW ON-RESISTANCE
SO-8
DESCRIPTION
This MOSFET is the second generation of STMicroelec-
tronis unique "Single Feature Size鈩?quot; strip-based pro-
cess. The resulting transistor shows extremely high
packing density for low on-resistance, rugged avalanche
characteristics and less critical alignment steps therefore
a remarkable manufacturing reproducibility.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
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DC MOTOR DRIVES
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AUDIO AMPLIFIER
Ordering Information
SALES TYPE
STS3C2F100
MARKING
S3C2F100
PACKAGE
SO-8
PACKAGING
TAPE & REEL
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(
鈥?
P
tot
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k
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)
Gate- source Voltage
Drain Current (continuous) at T
C
= 25擄C
Drain Current (continuous) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Storage Temperature
Max. Operating Junction Temperature
N-CHANNEL
100
100
鹵 20
3.0
1.9
12
2
-55 to 150
150
1.5
1.0
6
P-CHANNEL
Unit
V
V
V
A
A
A
W
擄C
擄C
(
鈥?
Pulse width limited by safe operating area.
June 2004
.
Note: P-CHANNEL MOSFET actual polarity of voltages and current
has to be reversed
Rev.1.0.1
1/11
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