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STS1HNC60 Datasheet

  • STS1HNC60

  • N-CHANNEL 600V - 7ohm - 0.4A SO-8 PowerMesh⑩II MOSFET

  • 6頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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STS1HNC60
N-CHANNEL 600V - 7鈩?- 0.4A SO-8
PowerMesh鈩I MOSFET
PRELIMINARY DATA
TYPE
STS1HNC60
s
s
s
s
s
V
DSS
600 V
R
DS(on)
<8
鈩?/div>
I
D
0.36 A
TYPICAL R
DS
(on) = 7
鈩?/div>
EXTREMELY HIGH dv/dt CAPABILITY
100% AVALANCHE TESTED
NEW HIGH VOLTAGE BENCHMARK
GATE CHARGE MINIMIZED
SO-8
DESCRIPTION
Using the latest high voltage MESH OVERLAY鈩I
process, STMicroelectronics has designed an ad-
vanced family of power MOSFETs with outstanding
performances. The new patent pending strip layout
coupled with the Company鈥檚 proprietary edge termi-
nation structure, gives the lowest RDS(on) per area,
exceptional avalanche and dv/dt capabilities and
unrivalled gate charge and switching characteris-
tics.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
s
SWITCH MODE LOW POWER SUPPIES
(SMPS)
s
CFL
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(
q
)
P
TOT
dv/dt(1)
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuos) at T
C
= 25擄C
Drain Current (continuos) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Derating Factor
Peak Diode Recovery voltage slope
Storage Temperature
Max. Operating Junction Temperature
Value
600
600
鹵 30
0.36
0.22
1.44
2.5
0.028
3.5
鈥?5 to 150
150
(1)I
SD
鈮?/div>
0.36 A, di/dt
鈮?00A/碌s,
V
DD
鈮?/div>
V
(BR)DSS
, T
j
鈮?/div>
T
JMAX.
Unit
V
V
V
A
A
A
W
W/擄C
V/ns
擄C
擄C
(鈥?Pulse width limited by safe operating area
July 2001
1/6

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